IEEE Central Texas Section

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Basics of Digital PLLs

April 18 @ 10:00 am - 11:00 am

Co-sponsored by: Nagaraja Revanna

This tutorial will introduce the fundamentals of analysis and practical implementation of digital PLLs. Unlike analog loops, the design of digital PLLs should take into account quantization, which can potentially generate limit cycles and degrade the output spectrum. A full design flow to meet bandwidth and jitter specifications, avoiding limit cycles, will be illustrated, and a comparison between digital PLLs based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors, will be shown.

Speaker(s): Salvatore Levantino,

Location:
Room: EER 3.646
Bldg: EERC
2501 Speedway
Austin, Texas
78712

Details

Date:
April 18
Time:
10:00 am - 11:00 am
Website:
http://events.vtools.ieee.org/m/197888
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