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IEEE San Antonio Computer chapter: Soft-Core CPUs

April 17 @ 7:00 pm - 8:30 pm

One of the most exciting parts of learning VHDL or Verilog is creating a CPU of your own design.  Many college courses have this as a course project.  For others, it is a hobby.  Some designs have become widely used.  Some are used to implement early game machines. Some are commercial IP (Intellectual Property).  A soft-core processor can often be added to a FPGA project using spare chip capacity.

The speaker has gathered the source code of such designs and has completed a relatively complete classification of about 600 of them, with web links to a source repository where available (available at opencores.org/project,up_core_list).

Speaker(s): Jim Brakefield,

Location:
Room: 111
Bldg: Math
St. Mary’s University
San Antonio, Texas

Details

Date:
April 17
Time:
7:00 pm - 8:30 pm
Website:
http://events.vtools.ieee.org/m/170930
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