Internet in a chip

It is now at least ten years that chip manufacturers are trying to increase the processing power of chips by multiplying the cores, each one a processor in itself. This allows for parallel operations and a theoretical multiplication of processing capacity. It is a good approach since you can multiply the capacity without increasing hte clock speed and hence the power required…
The problem however is that in order to have parallel processing you need to have a problem that can be subdivided in parts that can be processed in parallel. And you need to have a practical way to program such parallelism in a manageable way.
There is also an additional issue, and that is to find a way to connect the various cores on the chip in such a way that they can operate independently of one another, when possibile and in cooperation when needed.
So far communications among the cores is ensured via a common bus connection all of them. The problem with this bus is that as the number of cores grow the contention on the bus grows too (since the bus has to be reserved by one core when it needs to communicate). 
Now researchers at MIT have revealed a chip with 36 cores interconnected via a miniaturised Internet that solve the contention issue as well as related cashing problems.
This is interesting also at a global architectural level since one could imagine that cores are interconnected among them in the chip through this mini internet and can be interconnected with other cores in other chips, in the same board or in boards on the other side of the Earth still using Internet and being programmed with the same software paradigm.
I can see in the future a super massive distributed processing architecture taking advantage of whatever processing capacity exist, transforming processing points into a processing fabric that will contain storage capacity and communications capacity, whre the local processing will be as relevant as the global processing. We have got a good example of this architecture and we take it around every day with us: our brain.

About Roberto Saracco

Roberto Saracco fell in love with technology and its implications long time ago. His background is in math and computer science. Until April 2017 he led the EIT Digital Italian Node and then was head of the Industrial Doctoral School of EIT Digital up to September 2018. Previously, up to December 2011 he was the Director of the Telecom Italia Future Centre in Venice, looking at the interplay of technology evolution, economics and society. At the turn of the century he led a World Bank-Infodev project to stimulate entrepreneurship in Latin America. He is a senior member of IEEE where he leads the New Initiative Committee and co-chairs the Digital Reality Initiative. He is a member of the IEEE in 2050 Ad Hoc Committee. He teaches a Master course on Technology Forecasting and Market impact at the University of Trento. He has published over 100 papers in journals and magazines and 14 books.