IEEE Future Directions
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Moore’s law of increasing integration has been over for a few years now, yet companies are still looking at ways of producing more effective chips and increasing integration is still a path to follow.
We have seen the evolution from monolithic chips with smaller and smaller etching (we are now below 10nm) to chips composed by smaller chips, chiplets, that you can plug like tiles of a puzzle. This leads to easer design of more complex chips but the surface gets bigger and bigger.
Now Intel has announced a new 3D architecture where chiplets can be stacked one on the other, leading to an increased integration where both space and power consumption are not increased.
The announcement took place at Intel Architecture Day, on December 11, 2018, showing the first 3D chip architecture for CPUs, code named Foveros.
3D architecture in chips is not new, most new memory chips are based on it and we already have several tens of layers of stacking. However, CPU stacking is completely new.
Intel intends to create a basic chip layer upon which, depending on needs, chiplets may be stacked on demand. This creates a very flexible manufacturing process that is also fostering innovation, since with this architecture innovation can be brought by a single chiplets, while today an innovation would require to work on the whole chip, making it more complicated and expensive. In a way it is like saying that the base layer is like a cellphone and the chiplets are like the apps that you can load on the cellphone. Seeing it in this way (although it is a bit an over-stretching of the concept) it is obvious the advantage of this architecture.
The plan is to have it available, with first chips being manufactured, in the second half of 2019, with the first chip using a low power 22FFL base (Fin Fet Low Power) with high performance compute-stacked chiplets
