IEEE Penang Joint Chapter


December 17th, 2017

Date:  January 5, 2018 (Friday)
Time:  2:30pm to 5:45pm
Location: PSDC, 1 Jalan Sultan Azlan Shah, 11900 Bayan Lepas, Penang

All are cordially invited to attend. Admission is FREE. Refreshment will be served.


2:30pm – 3:15pm A Novel Interconnect Material for the Challenges in High Speed and High Reliability Chips by Dr. Tan Cher Ming, Chang Gung University
3:15pm – 4:00pm High Performance Ge pMOSFET with Interfacial Layer Engineering by Prof. Kuei-Shu Chang-Liao, National Tsing Hua University
4:00pm – 4:15pm Tea Break
4:15pm – 5:00pm Future III-V/CMOS Co-Integrated Technology and Hybrid Circuit Design by Dr. Xing Zhou, Nanyang Technological University
5:00pm – 5:45pm Challenge on ESD Protection Design for SoC with Separated Power Domains by Prof. Ming-Dou Ker, National Chiao-Tung University

Distinguished Lecture 1 – A Novel Interconnect Material for the Challenges in High Speed and High Reliability Chips by Prof. Tan Cher Ming


Interconnections are the key link to all electronic circuitry. With the demand of higher speed and high reliability electronic systems, especially the 5G and IoT, the current interconnect resistance and reliability is too large to meet the demand. The electromagnetic interference (EMI) derived from the interconnections can also pose challenges. This talk presents a new development of interconnection which combine the conventional copper interconnects with graphene that can reduce the interconnect resistivity and enhances its reliability significantly. The impact of interconnect reliability on its EMI is also shown which demonstrate the necessity of considering interconnect reliability for high speed applications.

Distinguished Lecturer 1

Dr. Tan Cher Ming received his Ph.D in Electrical Engineering from the University of Toronto in 1992. He has 10 years of working experiences in reliability in electronic industry (both Singapore and Taiwan) before joining Nanyang Technological University (NTU) as faculty member in 1996 till 2014. He joined Chang Gung University, Taiwan and set up a research Center on Reliability Sciences and Technologies in Taiwan and acts as Center Director. He is Professor in Electronic Department of Chang Gung University, Honorary Chair Professor in Ming Chi University of Technology, Taiwan. He has published 300+ International Journal and Conference papers, and giving 10+ keynote talks and 50+ invited talks in International Conferences and several tutorials in International Conferences. He holds 12 patents and 1 copyright on reliability software. He has written 4 books and 3 book chapters in the field of reliability. He is an Editor of Scientific Report, Nature Publishing Group, an Editor of IEEE TDMR and Series Editor of SpringerBrief in Reliability. He is a member of the advisory panel of Elsevier Publishing Group. He is also in the Technical committee of IEEE IRPS. He is a past chair of IEEE Singapore Section, senior member of IEEE and ASQ, Distinguish Lecturer of IEEE Electronic Device Society on reliability, Founding Chair and current Chair of IEEE Nanotechnology Chapter – Singapore Section, Fellow of Institute of Engineers, Singapore, and Fellow of Singapore Quality Institute. He is the Founding Chair of IEEE International Conference on Nanoelectronics, General Chair of ANQ Congress 2014. He is also the recipient of IEEE Region 10 Outstanding Volunteer Award in 2011. He is Guest Editor of International J. of Nanotechnology, Nano-research letter and Microelectronic Reliability. He is in the reviewer board of several International Journals such as Thin Solid Film, Microelectronic Reliability, various IEEE Transactions, Reliability Engineering and System Safety etc for more than 5 years. He is the only individual recipient of Ishikawa-Kano Quality Award in Singapore since 2014. He is also current active in providing consultation to multi-national corporations on reliability. His research interests include reliability and failure physics modeling of electronic components and systems, finite element modeling of materials degradation, statistical modeling of engineering systems, nano-materials and devices reliability, and prognosis & health management of engineering system.

Distinguished Lecture 2 – High Performance Ge pMOSFET with Interfacial Layer Engineering by Prof. Kuei-Shu Chang-Liao


High performance Ge pMOSFETs are demonstrated by engineering interfacial layer. A Hf-rich buffer layer (HBL), GeON interfacial layer (IL) formed with NH3 plasma, and microwave annealing (MWA) are proposed to improve electrical characteristics of Ge MOSFET. A very high peak hole mobility of ~ 900 cm2/V-s, extremely low JG of ~ 10-5 A/cm2, and EOT of~ 0.5 nm in Ge pMOSFET are simultaneously achieved by the proposed IL treatments. The high performance can be attributed to the formation of high oxidation states in IL. The O-N polar covalent bonds in GeON are efficiently annealed by MWA to increase Ge oxidation sate in the IL. Ge out-diffusion or GeO
desorption can be suppressed by a MWA thanks to less thermal budget. Therefore, HBL, GeON IL, and MWA are promising process techniques for high performance Ge MOSFET.

Distinguished Lecturer 2

Kuei-Shu Chang-Liao received the B.S. and M.S. degrees in Telecommunication and Electronics from National Chiao Tung University, 1984 and 1989, respectively, and the Ph.D. degree in Electrical Engineering from National Taiwan University in 1992. In 1992, Dr. Chang-Liao joined the faculty at the National Tsing Hua University where he has been a Professor of Department of Engineering and System Science since 1999. In 2000, he was a visiting research fellow at the Department of Electrical Engineering of Yale University, where he was involved in Flash memory and charge pumping measurement. During 2007-2010, he served as the Associate Chairman of Department of Engineering and System Science. His current research interests include high-k/metal gate stack processes in FinFET, Ge or SiGe MOS devices, charge-trapping flash memory devices, and trap analysis in MOS device by charge pumping measurement. Dr. Chang-Liao is a Distinguished Lecture of IEEE EDS, senior member of IEEE, and member of the Electrochemical Society. He served as the Editor of IEEE Electron Device Letters during 2012-15. He received the excellent Industry-Academic Research Award from Ministry of Education in 2003. He has published over 300 papers in prestigious journals and conferences. He has chaired and served as committee members in several international conferences.

Distinguished Lecture 3 – Future III-V/CMOS Co-Integrated Technology and Hybrid Circuit Design by Dr. Xing Zhou


As Moore’s Law is slowing down and eventually approaching an end for conventional CMOS, new platforms for producing circuit-level innovation are desired. At the same time, it is not desirable to throw away the existing Si-CMOS infrastructure to start new. The SMART-LEES (Singapore MIT Alliance for Research and Technology – Low Energy Electronic Systems) program is such a “vertical” innovative platform by “inserting” III-V layers into a conventional Si-CMOS foundry process. This talk presents an overview of the SMART-LEES program as well as a unified compact model for generic GaN/InGaAs-based HEMTs in the context of the hybrid III-V + CMOS technology being developed for future heterogeneous integrated circuits. The developed model has been implemented in a hybrid III-V/CMOS foundry PDK for designing heterogeneous circuits in III-V/Si co-integrated technology.

Distinguished Lecturer 3

Dr. Xing Zhou obtained his B.E. degree in electrical engineering from Tsinghua University in 1983, M.S. and Ph.D. degrees in electrical engineering from the University of Rochester in 1987 and 1990, respectively. He has been with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore since 1992. His past research interests include Monte Carlo simulation of photocarrier transport and ultrafast phenomena as well as mixed-mode circuit simulation and CAD tool development. His recent research mainly focuses on nanoscale CMOS compact model development. His research group has been developing a unified core model for nanoscale bulk, SOI, double-gate, nanowire CMOS, as well as III-V HEMTs. He has given more than 140 IEEE EDS distinguished lectures and invited talks at various universities as well as industry and research institutions. He is the founding chair for the Workshop on Compact Modeling (WCM) in association with the NSTI Nanotechnology Conference since 2002. Dr. Zhou was an editor for the IEEE Electron Device Letters during 2007–2016, a guest Editor-in-Chief for the special issue of the IEEE Transactions on Electron Devices (Feb. 2014) on compact modeling of emerging devices, and a member of the Modeling & Simulation subcommittee for IEDM (2016, 2017). He has been an EDS distinguished lecturer since 2000.

Distinguished Lecture 4 – Challenge on ESD Protection Design for SoC with Separated Power Domains by Prof. Ming-Dou Ker


To reduce the weight of electronic products, to integrate more functions into the electronic products, as well as to reduce the power consumption of electronic products, the CMOS technology has been developed into nanometer scale to realize SOC for electronic systems. With the transistors in the nano-scale dimension, the gate-oxide thickness of MOSFET is only ~15Å for operating with sub-1V power supply. Such thinner gate oxide is very easily ruptured by electrostatic discharge (ESD) events, which frequently happen in our environments with the voltage level of hundreds or even thousands volts. The integrated circuits (ICs) are weaker to sustain such ESD stresses during the assembly, testing, package, and the applications. Therefore, the on-chip ESD protection circuits must be equipped on the ICs against ESD stresses, including the Human Body Model (HBM) and Charged Device Model (CDM). How to design the on-chip ESD protection circuits to effectively protect the integrated circuits realized by the nano-scale CMOS devices is a quite difficult challenge to IC industry, especially in the SOC with separated power domains. In this talk, the ESD issue on SOC with separated power domains will be discussed and shown with some failure cases. The successful ESD protection design to overcome such issue will be presented. To effectively protect the SoC chip, the “global” ESD protection must be provided to discharge ESD current across the separated power lines, as well as the “local” ESD protection is also needed to limit the ESD transient overstress voltage on the interface circuits. Automatic CAD tool to find out the location and/or interconnect of interface circuits across the separated power domains in the whole chip layout is strongly desired. The layout tool to automatically insert the cell (or block) of local ESD protection circuit at the right location is still waiting for further development in IC industry. ESD protection for CMOS ICs is not only the process issue but also highly dependent to the design issue, which has been an important topic that the IC designers need to know.

Distinguished Lecturer 4

Ming-Dou Ker received the Ph.D. degree from National Chiao-Tung University, Hsinchu, Taiwan, in 1993. He ever worked as the Department Manager with the VLSI Design Division, Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan. Since 2004, he has been a Full Professor with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan. During 2008~2011, he was rotated to be Chair Professor and Vice President of I-Shou University, Kaohsiung, Taiwan. Now, he has been the Distinguished Professor in the Institute of Electronics, National Chiao-Tung University, Taiwan. He ever served as the Executive Director of National Science and Technology Program on System-on-Chip (NSoC) in Taiwan during 2010~2011; and the Executive Director of National Science and Technology Program on Nano Technology (NPNT) in Taiwan (2011~2015). During 2012~ 2015, he was the Dean of the College of Photonics, National Chiao-Tung University (NCTU), Taiwan. Currently, he is serving as the Director of the Biomedical Electronics Translational Research Center (BETRC), NCTU, working on biomedical electronics translational projects. In the technical field of reliability and quality design for microelectronic circuits and systems, he has published over 500 technical papers in international journals and conferences. He has proposed many solutions to improve the reliability and quality of integrated circuits, which have been granted with hundreds of U.S. patents and Taiwan patents. He had been invited to teach and/or to consult the reliability and quality design by hundreds of design houses and semiconductor companies in the worldwide IC industry. His current research interests include the circuits and systems for biomedical applications, as well as circuit-related reliability issue. Prof. Ker has served as member of the Technical Program Committee and the Session Chair of numerous international conferences for many years, including the IEEE Symposium on VLSI Circuits. He ever served as the Associate Editor for the IEEE Transactions on VLSI Systems, 2006-2007. He was the Founding President of Taiwan ESD Association. Currently, he is the Editor of IEEE
Transactions on Device and Materials Reliability, and Associate Editor of IEEE Transactions on Biomedical Circuits and Systems. In 2015, Prof. Ker received the Award for Outstanding Science and Technology Contribution, the Executive Yuan, Taiwan. Prof. Ker has been a Fellow of the IEEE since 2008.