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TNANO Special Issue – Defect and Fault Tolerance

IEEE Transactions on Computers & IEEE Transactions on Nanotechnology
Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

With increasing defect rates in highly scaled CMOS and emergence of alternative nanotechnology devices, defect and fault tolerance in VLSI and nanotechnology systems is of growing importance. The IEEE Transactions on Computers and IEEE Transactions on Nanotechnology seek original manuscripts for a Special Section on Defect and Fault Tolerance in VLSI Systems scheduled to appear in the issue of March 2016.

The submitted papers must describe original research which is not published nor currently under review by other journals or conferences. Extended conference papers should contain at least 40% new material and will pass through the normal review process.

Important Dates:

  • Submission deadline: February 1, 2015.
  • First decision to authors:    April 15, 2015.
  • Revision due (if needed):     May 15, 2015.
  • Final notification of acceptance/rejection:         July 15, 2015.
  • Publication material for final manuscripts due:        July 31, 2015.
  • Special section publication:  March issue of 2016.

More information on this special issue are available at this link:

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