2017 Officers -IEEE EDS Washington/Northern Virginia Chapter:
Joseph J. Kopanski, Chair
Joseph J. Kopanski received the B.S. degree in Applied Physics and the M.S. degree in Electrical Engineering and Applied Physics from Case Western Reserve University in 1982 and 1985, respectively. His thesis involved the development of semiconductor processing technology for silicon carbide MOSFETs and blue light emitting diodes. He joined the National Institute of Standards and Technology (then the National Bureau of Standards) in Gaithersburg, MD in 1985 where he is currently a member of the technical staff. His research interests are currently focused on using scanning probe techniques, such as scanning capacitance microscopy, tunneling atomic force microscopy, and scanning Kelvin force microscopy for electrical transport characterization of nanostructures and back end of the line characterization issues. He became Group Leader of the Advanced Device Reliability and Characterization Group, Engineering Physics Division of the NIST Physical Measurement Laboratory in 2015. Mr. Kopanski is also the director of the Electrical Engineering Summer Undergraduate Research Fellowship (SURF) program in the Physical Measurement Laboratory of NIST.
Tony Guo, Vice Chair
Dr. Tony Guo has worked in R&D and manufacturing in semiconductor industries for over 18 years. He began his semiconductor career at Philips as an application engineer for circuit/PCB design & firmware optimization from 1997 to 2001. From 2002 to 2005, he was a research assistant of Microelectronics Research Center in the University of Texas at Austin, developed wide bandgap SiC avalanche photodiode for single photon counting, with record low dark current. After graduation with a PhD degree in Electrical and Computer Engineering, he joined Micron Technology Virginia in 2006, holding different engineering positions for memory device technology transfer and manufacturing, such as FEOL/BEOL, or device owner on various memory devices (NAND/NOR/PCM/DRAM). He has experience on device characterization/modeling, yield prediction and improvement, device qualification and reliability improvement, and big data mining. He is currently a senior device engineer of Process Integration department at Micron.
Dr. Guo had published more than 15+ IEEE journal papers and 8 Micron TLP (Technical Leadership Program) papers. His 1st-author paper on PMOS NBTI improvement had been awarded as the best Micron TLP paper in 2014. He was awarded for IEEE LEOS student travel grant in 2005. As a senior member of IEEE EDS, he had actively involved in several EDS events such as IEEE Memory Days, and volunteered STEM events. He is a life member of Texas Exes.
Murty Polavarapu, Treasurer
Murty Polavarapu advises companies on defense microelectronics, with emphasis on radiation hardening and nanotechnology applications. Immediately prior he spent three decades making significant contributions to advanced semiconductor logic and memory devices for companies including BAE Systems, IBM, Lockheed Martin, Micron, and Toshiba. He holds eleven patents and received numerous awards including the BAE Systems Chairman’s Silver Award, Dominion Semiconductor President’s Award and IBM Outstanding Technical Achievement Award. He is a Fellow of Washington Academy of Sciences.
Mr. Polavarapu earned his Masters in Electrical Engineering from Howard University and his Masters in Technology Management from University of Pennsylvania. He is motivated to help young people learn and has a keen interest in developing future engineers through STEM activities; he served as a United States Peace Corps volunteer physics teacher in Fiji and co-founded a non-profit organization to help bring computers to schools in Ethiopia. Murty is an avid world traveler.
2016 Officers -IEEE EDS Washington/Northern Virginia Chapter:
John Zhang, Chair
Dr. John Zhang has ~16 years of experience in semiconductor process R & D, Memory Process Integration, New Technology Transfer and Yield Improvement in a high volume manufacturing Fab. He received his Ph.D. degree in Materials Science and Engineering from Clemson University, South Carolina in 2000. After graduation, he joined Micron Technology (Boise) Process R & D for Memory Process Technology development. In 2002, he moved to Micron Technology Virginia to help set up Micron’s first 300 mm pilot line Fab and transfer 200 mm DRAM process technology from R & D Fab to 300 mm volume production Fab in Virginia . Since 2002, he has been working in Process Integration group at Micron Technology Virginia to drive new technology transfer, yield improvement, device/process optimization, and cost reduction for multi-generation DRAM technology nodes. In addition to his experience in Semiconductor Process Integration for 110-30 nm DRAM technology nodes, his expertise also covers High K Dielectric, Ferroelectric and Piezoelectric Materials/Devices. Dr. Zhang authored or co-authored 3 US patents and published 14 technical papers in different peer-reviewed journals. He has been a Senior Member of the IEEE -Electron Devices Society since 2009. He is currently a Senior Process Integration Engineer at Micron Technology Virginia.