Previous Meetings & Programs


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Thursday, November 10, 2016

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Dr. Archambeault at our November 2016 meeting

Speaker: Bruce Archambeault, PhD

IBM, Raleigh NC

www.brucearch.com

 

Location: Compliance Testing, LLC
1724 S. Nevada Way, Mesa, AZ 85204
Phone 480.926.1775
www.compliancetesting.com

(See all event photos here.)  — all photos by Steve Schafer of Compliance Testing Lab in Mesa

 

Facts about Decoupling Capacitors and PCBs!

Our final meeting of 2016 was held on November 11th 2016 at Compliance Testing Labs in Mesa Arizona, in conjunction with the IEEE EMCS officer’s meeting in downtown Phoenix that weekend.

The evening began with the customary social hour and some mighty fine pulled pork, smoked chicken, beans, and coleslaw from Tom’s BBQ in Mesa.

The meeting began with some announcements from our chapter chairman, Glen Gassaway. He went over IEEE business, updates regarding our new website (including our new corporate sponsorship program) and the newly created job board. Glen also talked about our upcoming IEEE Phoenix Mini-Symposium coming up in April.  We then had the usual around the room introductions and who is hiring and who is looking for work.

Our speaker, Dr. Bruce Archambeault had prepared a lecture on “Facts about Decoupling Caps and PCB’s”. His presentation covered case studies for different effects of capacitance value, number of capacitors, capacitor density, and capacitor configuration. Multiple analyses showed the different effects of ground plane geometries.

Bruce spoke about the physical cause of inductance (current path), and identified each portion of overall path. He mentioned that the value of capacitance is not as important as the number of capacitors, as well as the series inductances of the traces and vias leading to the capacitors.  Significantly, the via connection configuration can dramatically influence inductance.  If power/ground-reference planes are deep in PCB stackup, capacitor placement has less impact than might be expected.

Design conclusions include keeping the PWR/GND plane pair close to IC minimizes LIC. Keeping capacitors close to the power layer minimize the inductance Ldecap from the capacitor to the power plane. The PWR/GND plane separation shall be as small as possible.   Placing caps under the IC can benefit the design if board is thin or the plane inductance is large.  Also, the ground plane closest to the power layer affects the response most, all other ground layers have very little influence.

Dr. Archambeault was kind enough to give us a copy of his presentation. His final note was “A ring is a current loop which creates inductance and is the root of all evil! After the talk, Glen Gassaway gave Bruce a custom Arizona coffee mug for his fine presentation!

We thank Compliance Labs for hosting and providing their facilities for this event.

The Phoenix Chapter meeting was held in conjunction with the November 2016 EMCS officers meeting

The ‘Chow Line’ was well stocked.

Glen Gassaway Talks Chapter Business

Bruce Archambeault Presents

Bruce Archambeault Presents

Brett Gassaway, Bob Scully and Glen Gassaway chatting before the Phoenix Chapter Meeting

Another well-attended Phoenix Chapter event at Compliance Labs in Mesa, AZ

The Phoenix Chapter’s Social Hour is always a big hit

 

 

 

 

Glen Gassaway presents Bruce Archambeault with a custom Arizona coffe mug after the presentation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(See all event photos here.)