IEEE Phoenix Section

Including Northern Arizona

IEEE
December 7th, 2016

Annual Banquet – Saturday, February 11th, 2017

Phoenix Airport Marriott, 1101 North 44th Street, Phoenix, Arizona 85008

Keynote Presentation

 Title: TBD

 Speaker: Dr. George Poste

Chief Scientist of Complex Adaptive Systems Initiative (CASI)

Regents Professor and Del E. Webb Chair in Health Innovation

Arizona State University

SkySong, 1475 N. Scottsdale Rd, Suite, 361, Scottsdale, Arizona 85257

Tel: 480.727.8661, Email: George.Poste@asu.edu

Abstract

Dr. George Poste is the Del E. Webb Professor of Health Innovation and Chief Scientist, The Complex Adaptive Systems Initiative (CASI) (http://www.casi.asu.edu) at Arizona State University (ASU). This program integrates research in genomics, synthetic biology and high performance computing to study the altered regulation of molecular networks in human diseases to develop new diagnostic tests for precision (personalized) medicine and the remote monitoring of health status using miniaturized body sensors and mobile devices. He assumed this post in 2009. From 2003 to 2009 he directed and built The Biodesign Institute at ASU.

He has published more than 350 research papers and edited 14 books on pharmaceutical technologies, cancer and infectious diseases. He has received honorary degrees in science, law and medicine for his research contributions.

He serves on the Board of Directors of Monsanto, Exelixis, Caris Life Sciences, and the Scientific Advisory Boards of the A. Alfred Taubman Medical Research Institute at the University of Michigan, Synthetic Genomics, and Haplogen GmbH. From 1992 to 1999, he was Chief Science and Technology Officer and President, R&D, of SmithKline Beecham (SB). During his tenure at SB, he was associated with the successful registration of multiple drug, vaccine and diagnostic products. In 2004 he was named “R&D Scientist of the Year” by R&D Magazine, in 2006 he received the Einstein award from the Global Business Leadership Council, and in 2009 he received the Scrip Lifetime Achievement award voted by the leadership of the global pharmaceutical industry.

He is a Fellow of the U.K. Royal Society, the Royal College of Pathologists and the U.K. Academy of Medicine, a former Distinguished Fellow at the Hoover Institution, Stanford University, a member of the Council for Foreign Relations, a Governor of the Bulletin of Atomic Scientists, and a member of the U. S. Institute of Medicine Board on Global Health. He has served as a member of the Defense Science Board of the U.S. Department of Defense and currently serves on advisory committees for several U.S. government agencies in defense, intelligence, national security and healthcare.

Speaker Biography

Dr. George Poste is the Del E. Webb Professor of Health Innovation and Chief Scientist, The Complex Adaptive Systems Initiative (CASI) (http://www.casi.asu.edu) at Arizona State University (ASU). This program integrates research in genomics, synthetic biology and high performance computing to study the altered regulation of molecular networks in human diseases to develop new diagnostic tests for precision (personalized) medicine and the remote monitoring of health status using miniaturized body sensors and mobile devices. He assumed this post in 2009. From 2003 to 2009 he directed and built The Biodesign Institute at ASU.

He has published more than 350 research papers and edited 14 books on pharmaceutical technologies, cancer and infectious diseases. He has received honorary degrees in science, law and medicine for his research contributions.

He serves on the Board of Directors of Monsanto, Exelixis, Caris Life Sciences, and the Scientific Advisory Boards of the A. Alfred Taubman Medical Research Institute at the University of Michigan, Synthetic Genomics, and Haplogen GmbH. From 1992 to 1999, he was Chief Science and Technology Officer and President, R&D, of SmithKline Beecham (SB). During his tenure at SB, he was associated with the successful registration of multiple drug, vaccine and diagnostic products. In 2004 he was named “R&D Scientist of the Year” by R&D Magazine, in 2006 he received the Einstein award from the Global Business Leadership Council, and in 2009 he received the Scrip Lifetime Achievement award voted by the leadership of the global pharmaceutical industry.

He is a Fellow of the U.K. Royal Society, the Royal College of Pathologists and the U.K. Academy of Medicine, a former Distinguished Fellow at the Hoover Institution, Stanford University, a member of the Council for Foreign Relations, a Governor of the Bulletin of Atomic Scientists, and a member of the U. S. Institute of Medicine Board on Global Health. He has served as a member of the Defense Science Board of the U.S. Department of Defense and currently serves on advisory committees for several U.S. government agencies in defense, intelligence, national security and healthcare.

Banquet Agenda

Registration / Social Hour:               5:00 PM – 6:00 PM

Sit-Down Dinner:                6:00 PM – 7:00 PM

Section Program:                 7:00 PM – 8:00 PM

Keynote Presentation:                        8:00 PM – 8:30 PM

Awards Presentation:                         8:30 PM – 9:15 PM

Change of Section Officers:               9:15 PM – 9:30 PM

Banquet Registration Fees

IEEE Members – All Categories:                                                      $60.00

IEEE Student Members:                                                                     $40.00

IEEE Member and Student Member Guests:                                 $60.00

IEEE Student Branch Table without Guests:                                 $400.00

IEEE Society Chapter / Affinity Group Table:                               $600.00

Corporate Sponsorship:                                                                     $1500.00

Banquet Registration Direct Link: https://events.vtools.ieee.org/meeting/edit/42498

Note:

  • IEEE Members of all categories including student members should list their membership numbers at the time of registration.
    • The membership should be current and will be checked against IEEE Member Data Base.
  • All tables seat ten attendees.
  • Student Member table for ten cost is for seating ten IEEE Student members.
    • Cost for guests seated at the Student Branch table is $60.00.
  • Corporate Sponsorship includes recognition in program, table of ten for dinner, and 6’ x 3’ space for a display.
  • For additional information about the banquet, access
    http://sites.ieee.org/phoenix/2015/10/09/ieee-phoenix-section-annual-banquet-2016/

Banquet Menu

 Social Hour

Appetizers

Spanakopita

Chicken Sate

Assorted Vegetable & Assorted Cheese Displays

Cash Bar

Guests to Buy Tickets from the Hotel Cashier sitting next to Bar and present to Bartender for the Desired Drink

Premium Brands @ $8.00 Each

Absolute, Beefeaters, Bacardi Silver, Jack Daniel’s, Dewar’s, Sauza Gold, & Canadian Club

Wine by the Glass @ $8.00 per Glass

Canyon Roads Chardonnay, Cabernet Sauvignon, or Merlot

Domestic Beer Selection @ $5.00 per Bottle

Bud, Bud Light, Miller Lite

Imported Beer Selection @ $6.00 per Bottle

Corona, Heineken, Amstel Light

Assortment of Juice, Soda & Bottled Water @ $3.50 Each

Specialty Beer Selection @ $6.00 per Bottle

Sam Adams, Non-Alcoholic Beer St. Pauli, & O’Douls

Dinner Menu

Salad

Strawberry Fields Dinner Salad

Chilled Spring Mix, Candied Pecans, Crumbled Maytag Bleu Cheese, with Raspberry Vinaigrette Dressing Sliced Strawberries, Mandarin Oranges

Served with Assorted Rolls & Butter

Entrees Chicken Mediterranean

Boneless Breast of Grilled Chicken with sun dried tomato pesto, roasted red & yellow peppers, fresh mozzarella cheese

Served with Roasted Asparagus & Roasted Baby Red Potatoes

OR

Sliced Roast Beef Strip

Served with Red Wine Demi Sauce, Roasted Asparagus & Roasted Baby Red Potatoes

OR

Grilled Filet of Salmon

Served with Dejon Cream Sauce, Roasted Asparagus & Roasted Baby Red Potatoes

OR

Vegetarian / Vegan: Grilled Balsamic Portabello Mushroom Stack

Served Over Garlic Mashed Potatoes, Roasted Asparagus & Roasted Baby Red Potatoes

Dessert

Cheesecake with Raspberry Sauce or Raspberry Sorbet (Vegan)

Served with Freshly Brewed Regulieee-phoenix-section-annaul-banquet-2017-announcement-12-7-2017-draftar & Decaffeinated Coffee & Hot Tea


November 15th, 2016

ieee-phoenix-section-cpmt-society-chapter-november-16-2016-meeting-prof-muhannad-s-bakir2.5D and 3D IC Technology for Electronic Microsystems: Design Considerations and Experimental Demonstrations

Dr. Muhannad S. Bakir

Professor, School of Electrical & Computer Engineering, Georgia Institute of Technology

ABSTRACT

http://sites.ieee.org/phoenix/files/2016/11/IEEE-Phoenix-Section-CPMT-Society-Chapter-November-16-2016-Meeting-Prof.-Muhannad-S.-Bakir.pdf

This presentation will address innovative interconnection and integration technologies for electronic microsystems. First, we discuss a highly scaled through-silicon via (TSV) technology for fine-grain heterogeneous electronic integration; we demonstrate TSVs with diameter of less than 1-micron for a wide range of applications. Next, we present innovative thermal solutions for 2.5D and 3D integration platforms using microfluidic cooling; the performance of a 28 nm CMOS FPGA with monolithic microfluidic cooling is demonstrated. Moreover, we analyze the thermal implication of silicon bridge technology in 2.5D systems. We also describe innovative ‘thermal isolation’ technologies in which thermal coupling between 3D IC stacks is minimized using an air-gap isolation and mechanically flexible interconnects. Lastly, an innovative sacrificial micro-fabricated self-alignment technology is also discussed as part of this application (sub-1 micron alignment accuracy is demonstrated without the use of a flip-chip bonder).

BIOGRAPHY

Dr. Muhannad Bakir is a Professor in the School of Electrical and Computer Engineering at Georgia Tech. His areas of interest include three-dimensional (3D) electronic system integration, advanced cooling and power delivery for 3D systems, biosensors and their integration with CMOS circuitry, and nanofabrication technology. Dr. Bakir is the recipient of the 2013 Intel Early Career Faculty Honor Award, 2012 DARPA Young Faculty Award, and 2011 IEEE CPMT Society Outstanding Young Engineer Award. In 2015, Dr. Bakir was elected by the IEEE CPMT Society to serve as a Distinguished Lecturer for a four-year term. Dr. Bakir and his research group have received more than twenty conference and student paper awards including five from the IEEE Electronic Components and Technology Conference (ECTC), four from the IEEE International Interconnect Technology Conference (IITC), and one from the IEEE Custom Integrated Circuits Conference (CICC). Dr. Bakir’s group was awarded the 2014 Best Paper of the IEEE Transactions on Components Packaging and Manufacturing Technology in the area of advanced packaging. Dr. Bakir is an Editor of IEEE Transactions on Electron Devices and an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology.


November 5th, 2016

The November 2016 edition of the IEEE Phoenix Section newsletter “Valley  Megaphone” is now available.  The issue includes all the information regarding IEEE-Phoenix Section and its Society Chapters. Download the PDF version from the link right here. The current and older editions of the Megaphone can always be found here.


October 26th, 2016

The IEEE Phoenix Section recognizes the contributions of members, non-members, society chapters, affinity groups, student branches, corporations, and educational institutions at the annual banquet. The next banquet is scheduled for Saturday, February 11th, 2017 at Phoenix Airport Marriott located at 1101 N. 44th Street, Phoenix, AZ 85008 from 5:30 PM to 9:30 PM (Tel: 602-273-7373).

The Section is pleased to issue a call for nominations for this year’s Section awards. The scope and purpose of the Section Awards Program is to plan, promote and implement IEEE award programs that recognize outstanding performance in furthering the objectives and professional aims of the IEEE Phoenix Section, the IEEE, and the IEEE-USA, and to stimulate others to pursue such achievements of excellence.

Read the rest of this entry »


October 26th, 2016

The IEEE Phoenix Section awards Student Scholarships to full-time graduate and undergraduate students who are IEEE student members. The applying student must attend a full academic year at a university in the Phoenix Section during 2016. The universities include Arizona State University, DeVry University, Embry-Riddle Aeronautical University, and Northern Arizona University.

The student must submit a completely filled application along with a financial aid statement; a one-page personal statement of achievements, interests, and goals; official transcripts of all college work; and two recommendation letters from the School’s faculty. The scholarships are awarded based on academic achievement, financial need, and service to the IEEE.

Read the rest of this entry »


October 16th, 2016

The October 2016 edition of the IEEE Phoenix Section newsletter “Valley  Megaphone” is now available.  The issue includes all the information regarding IEEE-Phoenix Section and its Society Chapters. Download the PDF version from the link right here. The current and older editions of the Megaphone can always be found here.


September 15th, 2016

SusTech 2016 invites undergraduate students to submit abstracts for the Student Poster Contest.

Students are invited to send in ideas or designs for developing projects/products supporting the sustainability topics areas of the Conference. The selected posters will be displayed during the SusTech 2016 Student Poster Session, on Sunday October 9, being held in Phoenix, Arizona, USA.

The deadline to submit poster abstractscall-for-abstracts-poster-sustech-2016 is midnight US Mountain Time, September 23,2016.

Notification of acceptance will be sent out within two days of submission.

WHO CAN PARTICIPATE?

Poster authors must be undergraduate or graduate students at the time of submission and may be members of a team comprising of up to four students. At least one student author must be an IEEE student member at the time of the submission of the poster to the Contest. The poster should be fully the work of the student or students and completed before they have received their respective engineering or scientific degree.

TOPICS OF INTEREST

  • Internet of Things – IOT (e.g.: Sensors, computing, control, communication, storage and drive electronics targeted for IOT applications, medical electronics, drones)
  • Smart Grid (e.g. communication, control, power electronics, energy storage, demand control and response)
  • Waste: (e.g. reduction, conversion, disposal, recycling, reuse, harvesting, managing product lifecycle)
  • Renewable Energy (e.g. solar, wind, tidal, fuel cells, energy harvesting, nuclear, thermal, power distribution)
  • Water (e.g. Sourcing & distribution, conservation, harvesting, waste disposal, recycling)
  • Electronics (e.g. components and systems, sustainable manufacturing, automotive and industrial applications)
  • Energy Efficiency (e.g. sensing and measurement, energy saving, auto electrification & fuel economy, data centers)
  • Transportation (e.g. electric & autonomous vehicles, aviation, motors, drive controls, batteries)
  • Societal Implications / Quality of Life (e.g. global warming, sustainability education, human resources, risk-management, remediation, public policy)

HOW TO SUBMIT?

To participate in the contest students should write a 2-page (500-700-word) description (abstract) of the poster, along with authors names, respective university and contact details; and submit it using the SusTech website (include hyperlink here once weblink is created) by the specified deadline. The abstracts will be reviewed and authors notified by Sept 20th if they will be presenting at SusTech. If you have any questions or problems submitting your abstract, please contact session chairs Dr. Phani Vallabhajosyula, and Prof Michael Goryll at phani.c.v@ieee.org and michael.goryll@asu.edu. Contestants will need to prepare a poster of no larger than 48 x 36 inches and on a tri-fold board.

 

Key Dates Sept. 23, 2016 Submission deadline for poster abstract
Abstract Submission date + 2days Notification of Acceptance
Oct. 9, 2016 Final Poster Display During Conference

 PRIZES

Cash prizes will be awarded for first, second and third places as determined by the judges. First place $750; second $500; third $250. Information on the winners will be posted on the SusTech and IEEE Region 6 websites.

RULES REGARDING SUBMISSIONS

  1. Poster authors must be undergraduate or graduate students at the time of submission and may be members of a team comprising of up to four students.
  2. At least one student author must be an IEEE student member at the time of the submission of the poster to the Contest.
  3. The poster should be fully the work of the student or students and completed before they have received their engineering or scientific degree.
  4. The poster abstract should not be previously published or presented at another conference which has assigned copyright. If any plagiarism or copyright issues are found for the abstract, it will not be accepted.
  5. Poster abstracts must be submitted by the deadline. Abstracts submitted afterward will not be considered for evaluation.
  6. The organizing/review committee of the SusTech 2016 Student Poster Contest reserves the right to accept or reject any abstract without assigning any reason.

POSTER SPECIFICATIONS

  1. Posters must be tri-fold and may be no larger than 36”x48”
  2. Posters will be placed to stand alone on the tables

POSTER SESSION SCHEDULE AND SET UP FOR CONTESTANT

  1. Set up begins at 2:30 pm. At least one of the authoring students must be present at the SusTech Conference.
  2. Poster boards will be numbered.  Presenters should attach their posters to the board number corresponding to the number assigned to their poster.
  3. Judging will occur from 5:30-6:00pm.
  4. Poster session is open 3:00 pm – 7:00 pm.
  5. Take down by presenters no later than 7:10 pm.  Posters not removed by 7:10 pm will be taken to the Registration area.
  6. If selected as one of the winning posters, you will receive a ribbon on your poster and will also be notified via email.
  7. The SusTech Conference may request that prize posters be held temporarily for public display.

September 14th, 2016

The September 2016 edition of the IEEE Phoenix Section newsletter “Valley  Megaphone” is now available.  The issue includes all the information regarding IEEE-Phoenix Section and its Society Chapters. Download the PDF version from the link right here. The current and older editions of the Megaphone can always be found here.


September 8th, 2016

Tuesday, September 20th, 2016 at 5:30 PM

 On-Chip Embedded Cooling of Power and Logic Components

 Avram Bar-Cohen*, PhD – IEEE/CPMT Distinguished Lecturer

Principal Engineering Fellow, Raytheon Corporation – Sape & Airborne Systems, Rosslyn, Virginia,

abc@umd.edu

(*on Leave fromUniversity of Maryland, College Park, Maryland, USA)

 ABSTRACTieee-phoenix-section-cpmt-society-chapter-september-20

Thermal packaging technology has been a key enabler in the development of today’s microelectronic systems, including smart phones, tablet computers, back-room data-crunching supercomputers, and the navigation systems that have come to define our lives in the 21st Century. Much of the benefit that we derive from miniaturization, higher performance, lower cost and greater reliability of these quintessential 21st Century “widgets,” can be traced to improvements in thermal technology, thermal modeling, and the integration of thermal management principles and techniques into electronic product development.

A review of thermal packaging over the first 70 years of the Information Age will reveal a relentless “inward migration” of cooling technology from room ventilation and air-conditioning, to cabinet cooling, to component cooling with heat sinks and cold plates, and to today’s efforts to address on-chip hot spots and near-junction thermal transport. Attention will then be devoted to current thermal management requirements, driven by nano-electronics, which confront packaging engineers with the simultaneous “triple threat” of high-power, “hotspots,” and 3D integration in applications as diverse as high performance computing, power electronics, and RF systems. The lecture will close with a review of 3rd-generation thermal management technologies relying on intra- and interchip microfluidic cooling, use of diamond substrates, and on-chip thermoelectric coolers to implement the emerging “embedded cooling” paradigm. 

Date:           Tuesday, September 20th, 2016

Location:    Constellation Room, NXP Semiconductors, Discovery Business Center, 2108 E. Elliot Road, Tempe, Arizona..

Note New Address – Park on east side of campus – New main entrance on south side facing Elliot Road

Sign in at the security station to obtain visitor pass BEFORE 5:45 PM. Present Valid Photo ID.

You will be escorted to the meeting room. Within the building you should always be escorted..

Agenda:     5:30–6:00 PM: Social/Refreshments, 6:00–7:00 PM: Presentation, 7:00 PM: Dinner

(Pizza and Soda will be provided by the IEEE Phoenix Section CPMT Society Chapter)

IEEE members and non-members are all welcome to attend. The presentation promptly starts at 6:00 PM.


August 15th, 2016

IEEE Phoenix Section CPMT Society Chapter – August 17, 2016 Meeting – Dr. Katsuyuki Sakuma

 Dr. Katsuyuki Sakuma

Research Staff Member, IBM T.J. Watson Research Center

ABSTRACT

3D IC integration technology and large die packaging are essential ingredients for further performance enhancement of main frame and super-computer applications, but warpage of large and thin interposers is one of the biggest challenges in achieving large die 3D IC integration. In addition to that, a micro-bump pitch for 3D application is becoming smaller in order to achieve higher bandwidth I/Os, hence removal of flux residue becomes more difficult. To eliminate the use of flux and its associated cleaning process during flip chip bonding, a micro-scrub thermo-compression (TC) bonding process was evaluated as a potential bonding method. We also demonstrated a successful bonding process for large die 3D IC integration with 22 nm ULK CMOS technology by developing an enhanced TC bonding process that addresses problems caused by interposer and laminate warpage. Both TC bonding technologies will be discussed.

Wednesday, August 17th, 2016 at 5:30 PM