IEEE Phoenix Section

Including Northern Arizona

January 30th, 2018

IEEE Electronics Packaging Society (EPS) – Phoenix Chapter – February Meeting

 (Formerly Known as Components, Packaging and Manufacturing Technology (CPMT) Society)

Wednesday, February 28, 2018: 5:30 PM

Integrated Circuit Design for Miniature Implantable Medical Devices

Andrew Kelly,

IC/Systems Architect, Cactus Semiconductor Inc.

Chandler, AZ USA


A new generation of Miniature Implantable Medical Devices (MIMDs) has arrived. Thanks to technological advances in Micro-Electro-Mechanical Systems (MEMS), electronics packaging, integrated passive devices, and solid-state batteries, many of the typical elements within Implantable Medical Devices (IMDs) can be drastically miniaturized.  Custom Integrated Circuit (IC) design can then be employed to integrate these technologies – often with diverging requirements – to produce new devices that are a fraction of the size of traditional IMDs.

The new MIMDs are small enough to be implanted at the point of the sensing or therapy, thus eliminating the need for long leads, and enabling minimally invasive surgical procedures. These minimally invasive procedures reduce surgical complications, speed recovery, and drastically reduce costs.

This talk presents a comparison of MIMDs to traditional IMDs, summarizes several enabling technologies and unique design opportunities, and describes custom IC design approaches that capitalize on the available technologies and opportunities. Finally, the approaches are substantiated with a review of a recent MIMD development project that produced a complete Neuro-Stimulator device with a total device volume less than 1cc.


Andrew Kelly is an IC/Systems Architect at Cactus Semiconductor Inc. in Chandler, Arizona. Before joining Cactus Semiconductor, he was a Senior Principal IC Design Engineer at the Medtronic Microelectronics Center.  Over the past 30 years, he has defined and designed dozens of Full Custom Mixed-Signal ICs for a wide range of Portable, Wearable, and Implantable Medical Devices such as; Glucose Meters, Hearing Aids, Neuro-Stimulators, Drug Infusion Pumps, Bio Sensors, Orthopedic Sensors, and Cardiac Pacemakers.

Date:          Wednesday, February 28, 2018, 5:30 PM

Location:  Meeting Room B

                  Tempe Public Library

                  3500 S. Rural Road, Tempe, AZ 85282

                  (S-W corner of Rural & Southern Ave.)”/tempe+library/

Agenda:   5:30–6:00 PM: Networking & Refreshments,

                      6:00–7:00 PM: Presentation,

7:00 – 7:30 PM Questions & Answers

(Snacks and Soda will be provided by the IEEE Phoenix Section, CPMT Society Chapter)
IEEE members and non-members are all welcome to attend. The presentation promptly starts at 6:00 PM.

For more information, please contact any of the following CPMT officers:

Vasu Atluri           (480) 227-8411                                               Marc Licciardi  (650) 996-0478

Vivek Gupta         (480) 734-0266                                               David Dougherty             (480) 245-8099

Mahesh Shah      (480) 544-9438                                               Bharat Penmecha           (480) 552-2511

Rao Bonda            (480) 786-7749                                               Dinesh Thanu

October 9th, 2017

IEEE Electronics Packaging Society (EPS) – Phoenix Chapter

Formerly Known as Components, Packaging and Manufacturing Technology (CPMT) Society

Remember this meeting is on Monday, October 16, 2017, 5:30 PM

System in Package (SiP) Packaging Technology Trends

Vinayak Pandey

VP, Product & Technology Marketing

JCET-Stats ChipPAC Inc.

Tempe, AZ USA


System-in-package (SiP) technology has been evolving through utilization of various package technology building blocks to serve the market needs with respect to miniaturization, higher integration, and smaller form factor, with the added benefits of lower cost and faster time to market as compared to silicon (Si) level integration, which is commonly called SoC or system-on-chip. As such, SiP incorporates flip-chip (FC), wire bond (WB), and wafer-level packaging (WLP) as its technology building blocks, and serves various end applications in all markets. Several key technologies are available as viable alternatives to the traditional SiP using a laminate type of solutions. Advanced embedded Wafer Level Ball Grid Array (eWLB) technology provides a versatile platform for the semiconductor industry’s technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations. Molded Interconnect Substrate (MIS) is another technology that can enable integration while managing lower costs. This presentation will review the packaging technology advancements in SiP as well as new packaging technologies for SiP.


Vinayak Pandey, VP

Product & Technology Marketing

JCET-Stats ChipPAC Inc.

Vinayak Pandey is the Vice President of Product & Technology Marketing at STATS ChipPAC where he is responsible for driving advanced packaging and SiP marketing and business development in the US region. Vinayak has more than 10 years of experience in business development, marketing and product line management to support customers in a wide range of semiconductor markets. Prior to STATS ChipPAC, Vinayak worked several years at Intel Corporation in microprocessor packaging. He has an MBA from Arizona State University and a Master of Science degree in Engineering Mechanics from Virginia Tech.

Date:          Monday, October 16, 2017, 5:30 PM

Location:  Meeting Room B

                  Tempe Public Library

                  3500 S. Rural Road, Tempe, AZ 85282

                  (S-W corner of Rural & Southern Ave.)”/tempe+library/

Agenda:   5:30–6:00 PM: Networking & Refreshments,

                      6:00–7:00 PM: Presentation,

7:00 – 7:30 PM Questions & Answers

(Snacks and Soda will be provided by the IEEE Phoenix Section, EP Society Chapter) IEEE members and non-members are all welcome to attend. The presentation promptly starts at 6:00 PM.


For more information, please contact any of the following EPS  officers:

Vasu Atluri – (480) 227-8411     David Dougherty – (480) 413-6923       Vivek Gupta – (480) 734-0266

Bharat Penmecha – (480) 552-2511        Marc Licciardi  (650) 996-0478               Rao Bonda – (480) 786-7749

Mahesh Shah – (480) 544-9438


September 21st, 2017

SusTech 2017 Student Poster Contest – Abstract Submission Dead line extended to Sept. 28, 2017


1st Price – $750

2nd Price – $500

3rd Price – $250

For more information, abstract upload, and registration, please visit or see attached flyer or

Please contact: Poster Contest Chairs:

Dr.; +1-512-797-835

Student Poster Contest

Student Poster Contest


September 15th, 2017

IEEE Electronics Packaging Society (EPS) – Phoenix Chapter

Formerly Known as Components, Packaging and Manufacturing Technology (CPMT) Society

Wednesday, September 27, 2017: 5:30 PM


Advancements in High Density Fan-out and Heterogeneous Integration

by Curtis Zwenger, VP, Advance Package & Technology Integration, Amkor Technology, Inc.


An advanced high-density fan-out structure called Silicon Wafer Integrated Fan-out Technology (SWIFT®) incorporates conventional WLFO processes with leading-edge thin film patterning techniques to bridge the gap between TSV and traditional WLFO packages. The SWIFT methodology is designed to provide increased I/O and circuit density within a reduced footprint and profile for single and multi-die applications.  The unique characteristics of the SWIFT process enable the creation of innovative structures that address the need for IC integration in emerging mobile and networking applications.  This presentation will review the development of the SWIFT technology and its extension into high performance 2D and 3D structures.  In addition, the advantages of SWIFT designs will be reviewed in comparison to current competing packaging technologies and to illustrate how the SWIFT is poised to provide robust, reliable, and low-cost packaging solutions for advanced mobile and networking products.

SWIFT is a registered trademark of Amkor Technology, Inc.


Curtis Zwenger, VP Adv. Package & Technology Integration    Amkor Technology

Curtis joined Amkor in 1999 and has held leadership roles in developing Amkor’s Fine Pitch Copper Pillar, Through Mold Via, and MEMS packaging technologies. He is currently responsible for the development and commercialization of Amkor’s Advanced Wafer Level Fan-Out package technologies, including WLFO and SWIFT®.  Prior to joining Amkor, Curtis worked for Motorola. He holds a degree in mechanical engineering from Colorado State University and an MBA from the University of Phoenix.


September 15th, 2017


IEEE Electronics Packaging Society (EPS) – Phoenix Chapter,

(Formerly Known as CPMT Society)

Wednesday, September 20, 2017: 5:30 PM


Innovation Roadmapping: Proven process to deliver Innovation to market

Yani Deros, President & Co-founder

ATOM Innovation + Product Development


Delivering the right innovation to any market is no small task in today’s fast paced and connected world. Expectations are high and everyone has a voice and opinion that can be the difference between a product success or failure. Find out how ATOM, a full-service product innovation firm based in Scottsdale, transforms the unique challenges each seed idea/concept through a comprehensive development methodology utilizing their proven Roadmapping process. Understand the formula and critical dynamics of validating the real problems needing to be solved. Tap into the “Voice of the Consumer/Customer” harvesting key insights to establish the product requirements and specifications to define the product development plan. Embrace iterative prototyping (hardware/electronics/UI) and user testing to optimize the user experience as an insurance policy often overlooked to mitigate unnecessary production delays, re-tooling, overruns and failures that adversely derail corporate objectives. Ultimately realize how the encompassing orchestration of shaping technology, electronics, product design and usability is skillfully applied to a Design for Manufacturing solution that can deliver on the expectations – market launch and bottom line revenue!


Yani Deros is an Innovation leader and visionary with 26+ years of experience developing advanced product and technology solutions for start-ups to global corporations. Yani has built ATOM into an internationally recognized and acclaimed product innovation firm specializing in the commercialization of emerging technologies and markets with a majority of their programs including electronics integration.

He has been the nucleus of many extraordinary development programs for some of the largest brands in the world providing creative leadership and a sound development philosophy that has delivered first-to-market and disruptive solutions across a wide range of industries.

ATOM has become one of the most proficient innovation firms in the country having developed over 280+ products and technology solutions in the last 14+ years that have resulted in almost $3B in durable goods orders over that timeframe.

Additionally, Yani has played an instrumental role in helping companies raise over $125 million in venture capital related to his technical and development contributions. His creativity has been honored by many of the most prestigious international product awards in addition to the 65+ U.S. and International patents received to date.

April 30th, 2017

Challenges and Approaches to Inductively Powering Integrated Passive Single-Chip RFID/Sensor Systems

Prof. L. Richard Carley,

Electrical & Computer Engineering Department

Carnegie Mellon University

Pittsburg, PA, USA



The design of fully integrated RFID/Sensor Systems, ones in which the antenna, the RFID circuitry, and the sensor circuitry are all fabricated on the same integrated circuit substrate, is challenging because the small size of the antenna and its proximity to a resistive ground plane (the integrated circuit substrate) both decrease the RF energy that can be harvested to operate the passive sensor system.  This presentation will present simplifying approximations in order to develop basic equations framing the challenges faced by fully integrated RFID/sensor systems in terms of harvesting energy posed by the size and geometry of the antenna and its proximity to the conductive silicon substrate.  These near-field equations will be validated for a practical design example with electromagnetic field simulations and strategies for improving energy harvesting performance will be discussed. Finally, the presentation will examine the challenging issue of matching the antenna to the on-chip electronics and efficiently converting it to a voltage that can power on-chip circuitry.  The presentation will end with a brief discussion of some potential applications of this new technology.


Richard Carley (S’74-M’84-SM’90-F’97) received an S.B. in 1976, an M.S. in 1978, and a Ph.D. in 1984, all from the Massachusetts Institute of Technology.  He joined the Electrical and Computer Engineering Department at Carnegie Mellon University (CMU) in Pittsburgh Pennsylvania in 1984, and in March 2001, he became the STMicroelectronics Professor of Engineering at CMU.  Dr. Carley’s research interests include analog and RF integrated circuit design in deeply scaled CMOS technologies, and novel micro-electro-mechanical and nano-electro-mechanical device design and fabrication.  For the past several years, Dr. Carley has studied the design of efficient RF energy harvesting devices in sub-millimeter RFID scenarios. Dr. Carley has been granted 24 patents, authored or co-authored over 200 technical papers, and authored or co-authored over 20 books and/or book chapters.  He has won numerous awards including Best Technical Paper Awards at both the 1987 and the 2002 Design Automation Conference (DAC), a “Most Influential Paper” award from DAC, and the “Best Panel Session” award at ISSCC in 1993.  In 1997, Dr. Carley co-founded the analog electronic design automation startup, Neolinear, which was acquired by Cadence in 2004. Dr. Carley has served on various conference program committees (e.g., CICC, ISLPED, and TMRC), was Associate Editor of IEEE Transactions on Circuits and Systems from 1993-1996, and was the General Chairman for RFID-TA 2016 in Shunde, China. Dr. Carley is currently a Distinguished Lecturer for the IEEE Council on RFID.


Date:          Wednesday, May 10, 2017, 5:30 PM


Meeting Room B

Tempe Public Library

3500 S. Rural Road, Tempe, AZ 85282

(S-W corner of Rural & Southern Ave.)”/tempe+library/


Agenda:   5:30–6:00 PM: Networking & Refreshments,

                      6:00–7:00 PM: Presentation,

7:00 – 7:30 PM Questions & Answers

(Snacks and Soda will be provided by the IEEE Phoenix Section, CPMT Society Chapter)

IEEE members and non-members are all welcome to attend. The presentation promptly starts at 6:00 PM.

For more information, please contact any of the following CPMT officers:


Vasu Atluri                 (480) 227-8411                Rao Bonda            (480) 786-7749               David Dougherty     (480) 413-6923

Vivek Gupta               (480) 734-0266                 Marc Licciardi    (650) 996-0478               Bharat Penmecha   (480) 552-2511

Mahesh Shah            (480) 544-9438


April 30th, 2017

IEEE Council for RFID (CRFID) Hosts Young Professionals Educational & Networking Event Phoenix, May 10, 2017

IEEE RFID YP Special Event Invitation

The IEEE Council for RFID and IEEE Young Professionals invite you to join us in Phoenix during the IEEE RFID 2017 and RFID Journal LIVE! Conferences for an afternoon of education followed by a networking reception on May 10th.

Complimentary Registration includes:

Exclusive Access to RFID Journal LIVE! Exhibition Area (3:005:00 pm)

Poster Competition Discuss technical research with IEEE RFID poster authors

Smart Cities MegaChallenge Listen to Finalists presentations

Exhibit Hall Explore the Exhibit Hall and See the latest industry innovations

YP Networking Reception Continue the conversation with your peers at Canyon Cafe (5:006:30)

The 11th Annual IEEE RFID 2017 and the 15th Annual RFID Journal LIVE! conferences will be held at the Phoenix Convention Center from May 911, 2017. The annual IEEE RFID conference represents multiple disciplines and highlights technical research and academia, while the RFIDJournalLIVE! conference is the world’s largest event focused on RFID and showcases over 200 exhibitors including; Honeywell, Impinj, NXP, RAIN RFID and Zebra.

Limited availability — Register Today


April 30th, 2017

11th Annual IEEE International Coference on RFID, May 9 – 11, 2017

Phoenix Convention Center, Phoenix AZ,

The IEEE Technical Council for RFID (CRFID) invites the IEEE Phoenix Section to converge at the 2017 IEEE International Conference (IEEE RFID 2017) -11, 2017 at the Phoenix Convention Center. The 11th annual

multi-disciplinary RFID conference is held in conjunction with RFID Journal LIVE! and provides academic and industry

perspectives from around the world and facilitates face-to-face interaction with the top researchers and scientists

working on RFID.

Program Topic/Specialty Areas

Antennas & Propagation – Antenna Theory & Designs, Channel Measurements and Modeling, including MIMO, UWB and Hybrid RFID

Applications & Software – RFID Software, middleware, network applications, various applications of RFID in Smart Cities,, Scientific Studies on operational experience of RFID applications, unconventional RF “identification”

Circuits, Devices & Readers – Circuit designs, radar architecture, non-silicon and chipless RFID, multi-reader co-ordination and interference reduction

Energey Harvesting & Wireless Power – Ambient RF Harvesting, Efficiency improvements, power-optimized waveforms, kinetic, thermal, optical and other power-harvesting methods

Internet of Thingss (IoT) & Next-Gen Physical Layer – RFID-enabled devices, IoT/RFID system architectures, MIMO, hybrid and UWB RFID systems novel networking and communication concepts

Localization – Performance bounds, novel system approaches, technoloogies and algoriths in RFID tag and radar localization, RF tomography and environmental sensing

Protocols & Security – Coding anti-collision, cryptography and privacy-enhancing techniques, medimum/multiple access schenes

Sensors – Integration of sensors with RFID tags, including active, passive or chipless mechanisms; RFID sensor molding and analysis, new sensors for RFID

Smart Cities – RFID system designs for smart citiesincluding data minimg, smart grids management, traffic flow control, mass transit monitoring nfrastructure support, revenue collections, parks management. The use of RFID is smart cities.

What to Expect from IEEE RFID 2017

Gain Experience from leading experts during interactive and hands-on Workshops and Tutorials

Receive Insight on the highest quality, original, high-impact research results in RFID-related topics

Acquire Knowledge on the latest and newest RFID-related work presented during the Poster Session

Engage in Discussion with the IEEE CRFID Smart Cities Mega-Challenge finalists’ as they present their RFID Smart

Cities Proposals

IEEE RFID YP Special Event Invitation Network with Your Peers at the IEEE RFID Young Professionsla Meet-Up and the Annual Networking Dinner. Kick

back and relax with other conference attendees, industry and academicians.

2017 IEEE RFID Keynote Speakers

Don’t miss these respected thought leaders expanding on key research and innovation about today’s most relevant RFID

and RFID related systems topics in this constantly evolving technology that is being widely implemented to solve local

and global problems in multiple disciplines and specialty areas.

Secure RFID for Trusting Devices and Data – Dr. Rene Martinez, Honeywell

Near Zero Power Radio Frequency Receivers – Dr. (Troy) Roy H Olssen III, DARPA

Special Access to RFID Journal LIVE!

The IEEE RFID 2017 conference is co-located with the RFID Journal LIVE! this year and your IEEE registration provides

special access to many LIVE! networking events and sessions including the opening reception, awards, and exhibition.

Register to attend IEEE RFID 2017 and RFID Journal LIVE!

April 9th, 2017

IEEE Phoenix Section is looking for Volunteers to fill following positions

  • Publicity Chair – Responsible to publish the monthly news letter Valley Megaphone and post it on Section Website and send link to all active members in Phoenix Section
  • We are also looking for volunteers to the position of Secretary as well as help with maintaining the website

If you are interested, please contact the Section Chair Surinder Tuli at