IEEE Phoenix Section

Including Northern Arizona

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Archive for the ‘Announcements’ Category

IEEE Phoenix Section Student Scholarships For The Year 2016

Thursday, December 29th, 2016

Please Submit the Scholarship Application at the Link below:

IEEE Phoenix Section Student Scholarships For The Year 2016

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The IEEE Phoenix Section awards Student Scholarships to full-time graduate and undergraduate students who are IEEE student members. The applying student must attend a full academic year at a university in the Phoenix Section during 2016. The universities include Arizona State University, DeVry University, Embry-Riddle Aeronautical University, and Northern Arizona University.

The student must submit a completely filled application along with a financial aid statement; a one-page personal statement of achievements, interests, and goals; official transcripts of all college work; and two recommendation letters from the School’s faculty. The scholarships are awarded based on academic achievement, financial need, and service to the IEEE.

The IEEE Phoenix Section will present the following Student Scholarship awards at the annual banquet scheduled for Saturday, February 11th, 2017 at Phoenix Airport Marriott located at 1101 N. 44th Street, Phoenix, AZ 85008 from 5:30 PM to 9:30 PM (Tel: 602-273-7373):

“Atluri Award” sponsored by Dr. Vasudeva Prasad Atluri and Dr. Satyavathi Atluri. Total of two award recipients are presented with a plaque and a check for $1000.00 each. Only graduate students are eligible for these awards.

“Al Gross Award” sponsored by IEEE Components, Packaging, and Manufacturing Technology (CPMT) Society Phoenix Chapter. The award recipient is presented with a plaque and a check for $1000.00. Graduate and undergraduate students are eligible for this award.

“Irv Kaufman Award” sponsored by IEEE Waves and Devices Phoenix Chapter. The award recipient is presented with a plaque and a check for $1000.00. Graduate and undergraduate students are eligible for this award.

“Dieter Schroder Award” sponsored by IEEE Phoenix Section. The award recipient is presented with a plaque and a check for $1000.00. Graduate and undergraduate students are eligible for this award.

The checks for these four awards are given out from the IEEE Phoenix Section Student Scholarship Endowment administered by the IEEE Foundation. To learn more about IEEE Foundation, access http://www.ieeefoundation.org/.

Only applications received by the deadline, Wednesday, January 11th, 2017, will be reviewed by the awards committee consisting of the following IEEE Phoenix Section Officers:

Awards Committee Chair: Dr. Vasudeva P. Atluri

Awards Committee Vice-Chair: Dr. Charles E. Weitzel

Past Chair: Ms. Barbara McMinn

Chair: Mr. Bruce J. Ladewig

Vice Chair: Mr. Surinder K. Tuli

Secretary: Mr. Vivek Gupta

Treasurer: Dr. Mahesh K. Shah

Students Activities Coordinator: Dr. S. Diane Smith

Student scholarship winners, upon receiving notification from IEEE Phoenix Section Awards Committee, should send by email completely filled either Form W-9 for US Citizen or Form W-8 for Non-US Resident to Mr. Richard Allen, Senior Annual Giving & Data Integrity Specialist, IEEE Foundation, at richard.allen@ieee.org with a copy to Dr. Vasudeva P. Atluri, Section Awards Committee Chair, at vpatluri@ieee.org, by Sunday, January 22nd, 2017.

Key dates:

Submission Website Opens: Tuesday, November 1st, 2016

Application submission deadline: Sunday, January 11th, 2017

Scholarship recipients will be informed by: Wednesday, January 18th, 2017

Submit W-8 and W-9 Forms by: Wednesday, January 22nd, 2017

If you have any additional questions, please contact and Dr. Vasudeva P. Atluri, Section Awards Committee Chair, at (480) 227-8411 or by email at vpatluri@ieee.org and Dr. Charles E. Weitzel, Section Awards Committee Vice-Chair, at (480) 292-0531 or by email at c.weitzel@ieee.org.

ieee-phoenix-section-student-scholarships-announcement-for-the-year-2016-december-8-2016

IEEE Phoenix Section Awards For The Year 2016

Thursday, December 29th, 2016

Please Submit the Nomination Form at the link below:

IEEE Phoenix Section Awards For The Year 2016

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The IEEE Phoenix Section recognizes the contributions of members, non-members, society chapters, affinity groups, student branches, corporations, and educational institutions at the annual banquet. The next banquet is scheduled for Saturday, February 11th, 2017 at Phoenix Airport Marriott located at 1101 N. 44th Street, Phoenix, AZ 85008 from 5:30 PM to 9:30 PM (Tel: 602-273-7373).

The Section is pleased to issue a call for nominations for this year’s Section awards. The scope and purpose of the Section Awards Program is to plan, promote and implement IEEE award programs that recognize outstanding performance in furthering the objectives and professional aims of the IEEE Phoenix Section, the IEEE, and the IEEE-USA, and to stimulate others to pursue such achievements of excellence.

The Phoenix Section has established the following general award categories:

  • Member
·         Corporate
  • Society Chapter/Affinity Group
·         Educational
  • Non-member
·         Section Chair

The Awards Guide lists the awards along with the selection criteria that will be implemented for selecting the award recipient. The Awards Guide can be accessed at http://sites.ieee.org/phoenix/files/2013/10/IEEE-Phoenix-Section-Annual-Banquet-2014-Award-Nomination-Instructions-Ver.-1-Final.pdf.

Please read through the Awards Guide to help you in selecting the award category for nomination.

All sections of the form should be completely filled electronically. Submission of additional documents such as resume in support of the nomination is highly encouraged. 

Key Dates:

Submission Website Opens: Tuesday, November 1st, 2016

Submission deadline: Wednesday, January 11th, 2017

Awardees and nominators will be informed by: Wednesday, January 18th, 2017

Only nomination forms submitted by the deadline will be reviewed by the awards committee consisting of the following IEEE Phoenix Section Officers:

  • Awards Committee Chair: Dr. Vasudeva P. Atluri
  • Awards Committee Vice-Chair: Dr. Charles E. Weitzel
  • Past Chair: Ms. Barbara McMinn
  • Chair: Mr. Bruce J. Ladewig
  • Vice Chair: Mr. Surinder K. Tuli
  • Secretary: Mr. Vivek Gupta
  • Treasurer: Dr. Mahesh K. Shah
  • Student Activities Coordinator: Dr. Diane S. Smith

For additional information, please contact Dr. Vasudeva P. Atluri, Section Awards Committee Chair, at (480) 227-8411 or by email at vpatluri@ieee.org, and Dr. Charles E. Weitzel, Section Awards Committee Vice-Chair, at (480) 292-0531 or by email at c.weitzel@ieee.org.

ieee-phoenix-section-awards-announcement-for-the-year-2016-december-8-2016

 

Shaping the Career for the Next Generation Wireless Technologies

Thursday, December 29th, 2016

new-poster-2

IEEE MTT-S Young Professionals in Microwaves will be organizing a workshop on 16th January 2017 from 4:40pm-6:30 pm MST as a part of Radio Wireless Week 2017. The workshop will provide you a platform to share your knowledge with others, directly speak and network with the executives of the wireless industry. It’s a great opportunity to network and meet experts and young professionals all over phoenix.

Workshop will aim at: Shaping the Career for the Next Generation Wireless Technologies

Speakers:

  1. Paul Hart: Senior Vice President of RF Power at NXP Semiconductors
  2. Bob Sankman: Fellow, Intel
  3. Fred Schindler: Design Center Director, Qorvo
  4. Carl A. Davenport: General Manager of Product Development Engineering and Silicon Operations, IOT, Intel

Venue:

2nd level, Phoenix East West Room

Hyatt Regency

Phoenix, Arizona

Register now at this link: https://mttsyprww.eventbrite.ca

The registration fees for the event is $50. Register before January 1, 2017 using the promo code “MTTSYP” to avail a $40 off. If you have registered for the RWW conference, you do not need to register for the event separately.

ieee-mtt-s_yp

IEEE CPMT Society Meeting, Wednesday, November 16 2016

Thursday, November 10th, 2016

ieee-phoenix-section-cpmt-society-chapter-november-16-2016-meeting-prof-muhannad-s-bakir2.5D and 3D IC Technology for Electronic Microsystems: Design Considerations and Experimental Demonstrations

Dr. Muhannad S. Bakir

Professor, School of Electrical & Computer Engineering, Georgia Institute of Technology

ABSTRACT

http://sites.ieee.org/phoenix/files/2016/11/IEEE-Phoenix-Section-CPMT-Society-Chapter-November-16-2016-Meeting-Prof.-Muhannad-S.-Bakir.pdf

This presentation will address innovative interconnection and integration technologies for electronic microsystems. First, we discuss a highly scaled through-silicon via (TSV) technology for fine-grain heterogeneous electronic integration; we demonstrate TSVs with diameter of less than 1-micron for a wide range of applications. Next, we present innovative thermal solutions for 2.5D and 3D integration platforms using microfluidic cooling; the performance of a 28 nm CMOS FPGA with monolithic microfluidic cooling is demonstrated. Moreover, we analyze the thermal implication of silicon bridge technology in 2.5D systems. We also describe innovative ‘thermal isolation’ technologies in which thermal coupling between 3D IC stacks is minimized using an air-gap isolation and mechanically flexible interconnects. Lastly, an innovative sacrificial micro-fabricated self-alignment technology is also discussed as part of this application (sub-1 micron alignment accuracy is demonstrated without the use of a flip-chip bonder).

BIOGRAPHY

Dr. Muhannad Bakir is a Professor in the School of Electrical and Computer Engineering at Georgia Tech. His areas of interest include three-dimensional (3D) electronic system integration, advanced cooling and power delivery for 3D systems, biosensors and their integration with CMOS circuitry, and nanofabrication technology. Dr. Bakir is the recipient of the 2013 Intel Early Career Faculty Honor Award, 2012 DARPA Young Faculty Award, and 2011 IEEE CPMT Society Outstanding Young Engineer Award. In 2015, Dr. Bakir was elected by the IEEE CPMT Society to serve as a Distinguished Lecturer for a four-year term. Dr. Bakir and his research group have received more than twenty conference and student paper awards including five from the IEEE Electronic Components and Technology Conference (ECTC), four from the IEEE International Interconnect Technology Conference (IITC), and one from the IEEE Custom Integrated Circuits Conference (CICC). Dr. Bakir’s group was awarded the 2014 Best Paper of the IEEE Transactions on Components Packaging and Manufacturing Technology in the area of advanced packaging. Dr. Bakir is an Editor of IEEE Transactions on Electron Devices and an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology.

IEEE Phoenix Section Awards For The Year 2016

Wednesday, October 26th, 2016

The IEEE Phoenix Section recognizes the contributions of members, non-members, society chapters, affinity groups, student branches, corporations, and educational institutions at the annual banquet. The next banquet is scheduled for Saturday, February 11th, 2017 at Phoenix Airport Marriott located at 1101 N. 44th Street, Phoenix, AZ 85008 from 5:30 PM to 9:30 PM (Tel: 602-273-7373).

The Section is pleased to issue a call for nominations for this year’s Section awards. The scope and purpose of the Section Awards Program is to plan, promote and implement IEEE award programs that recognize outstanding performance in furthering the objectives and professional aims of the IEEE Phoenix Section, the IEEE, and the IEEE-USA, and to stimulate others to pursue such achievements of excellence.

(more…)

IEEE Phoenix Section Student Scholarships For The Year 2016

Wednesday, October 26th, 2016

The IEEE Phoenix Section awards Student Scholarships to full-time graduate and undergraduate students who are IEEE student members. The applying student must attend a full academic year at a university in the Phoenix Section during 2016. The universities include Arizona State University, DeVry University, Embry-Riddle Aeronautical University, and Northern Arizona University.

The student must submit a completely filled application along with a financial aid statement; a one-page personal statement of achievements, interests, and goals; official transcripts of all college work; and two recommendation letters from the School’s faculty. The scholarships are awarded based on academic achievement, financial need, and service to the IEEE.

(more…)

IEEE-CPMT Society, Phoenix Chapter Meeting, September 20, 2016

Thursday, September 8th, 2016

Tuesday, September 20th, 2016 at 5:30 PM

 On-Chip Embedded Cooling of Power and Logic Components

 Avram Bar-Cohen*, PhD – IEEE/CPMT Distinguished Lecturer

Principal Engineering Fellow, Raytheon Corporation – Sape & Airborne Systems, Rosslyn, Virginia,

abc@umd.edu

(*on Leave fromUniversity of Maryland, College Park, Maryland, USA)

 ABSTRACTieee-phoenix-section-cpmt-society-chapter-september-20

Thermal packaging technology has been a key enabler in the development of today’s microelectronic systems, including smart phones, tablet computers, back-room data-crunching supercomputers, and the navigation systems that have come to define our lives in the 21st Century. Much of the benefit that we derive from miniaturization, higher performance, lower cost and greater reliability of these quintessential 21st Century “widgets,” can be traced to improvements in thermal technology, thermal modeling, and the integration of thermal management principles and techniques into electronic product development.

A review of thermal packaging over the first 70 years of the Information Age will reveal a relentless “inward migration” of cooling technology from room ventilation and air-conditioning, to cabinet cooling, to component cooling with heat sinks and cold plates, and to today’s efforts to address on-chip hot spots and near-junction thermal transport. Attention will then be devoted to current thermal management requirements, driven by nano-electronics, which confront packaging engineers with the simultaneous “triple threat” of high-power, “hotspots,” and 3D integration in applications as diverse as high performance computing, power electronics, and RF systems. The lecture will close with a review of 3rd-generation thermal management technologies relying on intra- and interchip microfluidic cooling, use of diamond substrates, and on-chip thermoelectric coolers to implement the emerging “embedded cooling” paradigm. 

Date:           Tuesday, September 20th, 2016

Location:    Constellation Room, NXP Semiconductors, Discovery Business Center, 2108 E. Elliot Road, Tempe, Arizona..

Note New Address – Park on east side of campus – New main entrance on south side facing Elliot Road

Sign in at the security station to obtain visitor pass BEFORE 5:45 PM. Present Valid Photo ID.

You will be escorted to the meeting room. Within the building you should always be escorted..

Agenda:     5:30–6:00 PM: Social/Refreshments, 6:00–7:00 PM: Presentation, 7:00 PM: Dinner

(Pizza and Soda will be provided by the IEEE Phoenix Section CPMT Society Chapter)

IEEE members and non-members are all welcome to attend. The presentation promptly starts at 6:00 PM.

IEEE-CPMT Society, Phoenix Chapter Meeting, August 17, 2016

Monday, August 15th, 2016

IEEE Phoenix Section CPMT Society Chapter – August 17, 2016 Meeting – Dr. Katsuyuki Sakuma

 Dr. Katsuyuki Sakuma

Research Staff Member, IBM T.J. Watson Research Center

ABSTRACT

3D IC integration technology and large die packaging are essential ingredients for further performance enhancement of main frame and super-computer applications, but warpage of large and thin interposers is one of the biggest challenges in achieving large die 3D IC integration. In addition to that, a micro-bump pitch for 3D application is becoming smaller in order to achieve higher bandwidth I/Os, hence removal of flux residue becomes more difficult. To eliminate the use of flux and its associated cleaning process during flip chip bonding, a micro-scrub thermo-compression (TC) bonding process was evaluated as a potential bonding method. We also demonstrated a successful bonding process for large die 3D IC integration with 22 nm ULK CMOS technology by developing an enhanced TC bonding process that addresses problems caused by interposer and laminate warpage. Both TC bonding technologies will be discussed.

Wednesday, August 17th, 2016 at 5:30 PM

IEEE-CPMT Society Phoenix Chapter Meeting on Monday June 6, 2016

Sunday, June 5th, 2016

Understanding the Optical, Thermal, and Electrical Performances of LED and their Relationship to Efficiency of Solid-State Lighting

 Prof. Shi-Wei Ricky Lee, FIEEE, FASME, FIMAPS, FInstP

Professor of Mechanical & Aerospace Engineering, HKUST

Director of Center for Advanced Microsystems Packaging

Director of HKUST LED-FPD Technology R&D Center at Foshan

Senior Past-President of IEEE Components, Packaging and Manufacturing Technology Society

rickylee@ust.hk

 ABSTRACT

WYSIWYG (what you see is what you get) is an acronym in computer engineering to indicate the technology for matching the edited documents viewed on the monitor screen and its hardcopies in a printed format. In this presentation, I would like to illustrate a similar concept in LED packaging for solid-state lighting (SSL). LED has been claimed as the 4th generation light source which has the major merits of rather low power consumption and very long service life. Typical specifications include 150 lm/W and 50000 hours for luminous efficacy and operating life, respectively. However, it appears that not all people understand what these specifications refer to and imply. As a result, inappropriate expectation may occur due to misperception. In other words, what you see may not be what you thought. Consequently, such misunderstanding may hinder the propagation of LED for SSL. In this presentation, the essence in LED packaging to achieve WYSIWYT (what you see is what you thought) for SSL will be reviewed. Various topics on efficiencies and their corresponding loss channels at the LED package and luminaire levels will be discussed. Emphasis will be placed on the trends of LED packaging in order to achieve the intended performance.

BIOGRAPHY

Ricky Lee received his PhD degree from Purdue University in 1992. He joined the Hong Kong University of Science & Technology (HKUST) in 1993. During his career of tenure-track faculty at HKUST, Dr Lee once was on secondment to serve as Chief Technology Officer of Nano & Advanced Materials Institute (NAMI) for two and a half years. Currently Dr Lee is Professor of Mechanical Engineering and Director of Center for Advanced Microsystems Packaging (CAMP) at HKUST. He also has a concurrent appointment as Director of HKUST LED-FPD Technology R&D Center at Foshan, Guangdong, China. Due to his technical contributions, Dr Lee received many honors and awards over the years. In addition to being the recipient of 12 best/outstanding paper awards and 5 major professional society awards, Dr Lee is Life Fellow of ASME and IMAPS, and Fellow of IEEE and Institute of Physics (UK). He is also a Distinguished Lecturer and the Senior Past-President of the IEEE Components, Packaging, and Manufacturing Technology (CPMT) Society.

Date:             Monday, June 6th, 2016

Location:       Constellation Room, NXP Semiconductors, Discovery Business Center, 2108 E. Elliot Rd. Tempe, AZ.

                     Note New Address – Park on east side of campus – New main entrance on south side facing Elliot. 

                     Sign in at the security station to obtain visitor pass (Photo ID required) BEFORE 6:00 PM

You will be escorted to the meeting room. Please arrive at the entrance no later than 5:45 PM.

Agenda:        5:30–6:00 PM: Social/Refreshments, 6:00–7:00 PM: Presentation, 7:00 PM: Dinner

                     The presentation promptly starts at 6:00 PM.

(Pizza and Soda will be provided by the IEEE Phoenix Section CPMT Society Chapter)

IEEE members and non-members are all welcome to attend.

IEEE Phoenix Section CPMT Society Chapter – June 6, 2016 Meeting – Prof. Ricky S.W. Lee

IEEE-CPMT Phoenix Chapter – January, 20, 2016 Meeting – NEW ENTRANCE

Saturday, January 16th, 2016

Wednesday, January 20th, 2016 at 5:30 PM

PLEASE NOTE THE CHANGE OF ENTRANCE (SEE MAP BELOW)

Understanding and Managing the Key Cost Drivers in PCB Design to Optimize Performance and Cost

Marc Licciardi

CEO and Lead Engineer

DfX Engineering

Scottsdale, AZ 85254 USA

marc@dfxengineering.com

ABSTRACT

Printed circuit boards have become increasingly complex and diverse in their applications and design. Processing sequences can be over fifty steps long, leading to a number of design choices. While the process is complex, the fundamental cost drivers can be broken into a few significant categories. These categories can be translated into specific design goals, which can then inform the best cost-performance optimized design. This presentation will step you through the optimization process and highlight the cost and performance choices.

BIOGRAPHY

Marc Licciardi is the founder of DfX Engineering. His work focuses on supporting large OEMs to develop cost- and performance-optimized PCB designs for applications ranging from very high-volume consumer devices to high-reliability data center networking devices. Prior to founding DfX Engineering, he was an SVP at Gold Circuit Electronics in Taiwan. He also held design engineering roles at Adflex Solutions, Hughes Aircraft and Parlex Corporation. He has worked on flex, rigid flex, wafer probes, substrates, standard and HDI PCB’s. Licciardi holds a BSIE degree from Worcester Polytechnic Institute.

Date:             Wednesday, January 20st, 2016

Location:       Constellation Conference Room, NXP Semiconductor, Inc., Discovery Business Center, 2100 E. Elliot Rd. Tempe, AZ. Enter the facility through the Main (South) Lobby in building 94 and sign in with Security (Photo ID required) BEFORE 6:00 PM. You will be escorted to the meeting room. The presentation promptly starts at 6:00 PM.

Agenda:        5:30–6:00 PM: Social/Refreshments, 6:00–7:00 PM: Presentation, 7:00 PM: Dinner

(Pizza and Soda will be provided by the IEEE Phoenix Section CPMT Society Chapter)NXPTempe_Map

IEEE members and non-members are all welcome to attend. Please arrive at the facility entrance no later than 5:45 PM.