IEEE Phoenix Section

Including Northern Arizona

IEEE
December 29th, 2016

new-poster-2

IEEE MTT-S Young Professionals in Microwaves will be organizing a workshop on 16th January 2017 from 4:40pm-6:30 pm MST as a part of Radio Wireless Week 2017. The workshop will provide you a platform to share your knowledge with others, directly speak and network with the executives of the wireless industry. It’s a great opportunity to network and meet experts and young professionals all over phoenix.

Workshop will aim at: Shaping the Career for the Next Generation Wireless Technologies

Speakers:

  1. Paul Hart: Senior Vice President of RF Power at NXP Semiconductors
  2. Bob Sankman: Fellow, Intel
  3. Fred Schindler: Design Center Director, Qorvo
  4. Carl A. Davenport: General Manager of Product Development Engineering and Silicon Operations, IOT, Intel

Venue:

2nd level, Phoenix East West Room

Hyatt Regency

Phoenix, Arizona

Register now at this link: https://mttsyprww.eventbrite.ca

The registration fees for the event is $50. Register before January 1, 2017 using the promo code “MTTSYP” to avail a $40 off. If you have registered for the RWW conference, you do not need to register for the event separately.

ieee-mtt-s_yp


December 13th, 2016

The December 2016 edition of the IEEE Phoenix Section newsletter “Valley  Megaphone” is now available.  The issue includes all the information regarding IEEE-Phoenix Section and its Society Chapters. Download the PDF version from the link right here. The current and older editions of the Megaphone can always be found here.


November 10th, 2016

ieee-phoenix-section-cpmt-society-chapter-november-16-2016-meeting-prof-muhannad-s-bakir2.5D and 3D IC Technology for Electronic Microsystems: Design Considerations and Experimental Demonstrations

Dr. Muhannad S. Bakir

Professor, School of Electrical & Computer Engineering, Georgia Institute of Technology

ABSTRACT

http://sites.ieee.org/phoenix/files/2016/11/IEEE-Phoenix-Section-CPMT-Society-Chapter-November-16-2016-Meeting-Prof.-Muhannad-S.-Bakir.pdf

This presentation will address innovative interconnection and integration technologies for electronic microsystems. First, we discuss a highly scaled through-silicon via (TSV) technology for fine-grain heterogeneous electronic integration; we demonstrate TSVs with diameter of less than 1-micron for a wide range of applications. Next, we present innovative thermal solutions for 2.5D and 3D integration platforms using microfluidic cooling; the performance of a 28 nm CMOS FPGA with monolithic microfluidic cooling is demonstrated. Moreover, we analyze the thermal implication of silicon bridge technology in 2.5D systems. We also describe innovative ‘thermal isolation’ technologies in which thermal coupling between 3D IC stacks is minimized using an air-gap isolation and mechanically flexible interconnects. Lastly, an innovative sacrificial micro-fabricated self-alignment technology is also discussed as part of this application (sub-1 micron alignment accuracy is demonstrated without the use of a flip-chip bonder).

BIOGRAPHY

Dr. Muhannad Bakir is a Professor in the School of Electrical and Computer Engineering at Georgia Tech. His areas of interest include three-dimensional (3D) electronic system integration, advanced cooling and power delivery for 3D systems, biosensors and their integration with CMOS circuitry, and nanofabrication technology. Dr. Bakir is the recipient of the 2013 Intel Early Career Faculty Honor Award, 2012 DARPA Young Faculty Award, and 2011 IEEE CPMT Society Outstanding Young Engineer Award. In 2015, Dr. Bakir was elected by the IEEE CPMT Society to serve as a Distinguished Lecturer for a four-year term. Dr. Bakir and his research group have received more than twenty conference and student paper awards including five from the IEEE Electronic Components and Technology Conference (ECTC), four from the IEEE International Interconnect Technology Conference (IITC), and one from the IEEE Custom Integrated Circuits Conference (CICC). Dr. Bakir’s group was awarded the 2014 Best Paper of the IEEE Transactions on Components Packaging and Manufacturing Technology in the area of advanced packaging. Dr. Bakir is an Editor of IEEE Transactions on Electron Devices and an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology.


November 5th, 2016

The November 2016 edition of the IEEE Phoenix Section newsletter “Valley  Megaphone” is now available.  The issue includes all the information regarding IEEE-Phoenix Section and its Society Chapters. Download the PDF version from the link right here. The current and older editions of the Megaphone can always be found here.


October 26th, 2016

The IEEE Phoenix Section recognizes the contributions of members, non-members, society chapters, affinity groups, student branches, corporations, and educational institutions at the annual banquet. The next banquet is scheduled for Saturday, February 11th, 2017 at Phoenix Airport Marriott located at 1101 N. 44th Street, Phoenix, AZ 85008 from 5:30 PM to 9:30 PM (Tel: 602-273-7373).

The Section is pleased to issue a call for nominations for this year’s Section awards. The scope and purpose of the Section Awards Program is to plan, promote and implement IEEE award programs that recognize outstanding performance in furthering the objectives and professional aims of the IEEE Phoenix Section, the IEEE, and the IEEE-USA, and to stimulate others to pursue such achievements of excellence.

Read the rest of this entry »


October 26th, 2016

The IEEE Phoenix Section awards Student Scholarships to full-time graduate and undergraduate students who are IEEE student members. The applying student must attend a full academic year at a university in the Phoenix Section during 2016. The universities include Arizona State University, DeVry University, Embry-Riddle Aeronautical University, and Northern Arizona University.

The student must submit a completely filled application along with a financial aid statement; a one-page personal statement of achievements, interests, and goals; official transcripts of all college work; and two recommendation letters from the School’s faculty. The scholarships are awarded based on academic achievement, financial need, and service to the IEEE.

Read the rest of this entry »


October 16th, 2016

The October 2016 edition of the IEEE Phoenix Section newsletter “Valley  Megaphone” is now available.  The issue includes all the information regarding IEEE-Phoenix Section and its Society Chapters. Download the PDF version from the link right here. The current and older editions of the Megaphone can always be found here.


September 15th, 2016

SusTech 2016 invites undergraduate students to submit abstracts for the Student Poster Contest.

Students are invited to send in ideas or designs for developing projects/products supporting the sustainability topics areas of the Conference. The selected posters will be displayed during the SusTech 2016 Student Poster Session, on Sunday October 9, being held in Phoenix, Arizona, USA.

The deadline to submit poster abstractscall-for-abstracts-poster-sustech-2016 is midnight US Mountain Time, September 23,2016.

Notification of acceptance will be sent out within two days of submission.

WHO CAN PARTICIPATE?

Poster authors must be undergraduate or graduate students at the time of submission and may be members of a team comprising of up to four students. At least one student author must be an IEEE student member at the time of the submission of the poster to the Contest. The poster should be fully the work of the student or students and completed before they have received their respective engineering or scientific degree.

TOPICS OF INTEREST

  • Internet of Things – IOT (e.g.: Sensors, computing, control, communication, storage and drive electronics targeted for IOT applications, medical electronics, drones)
  • Smart Grid (e.g. communication, control, power electronics, energy storage, demand control and response)
  • Waste: (e.g. reduction, conversion, disposal, recycling, reuse, harvesting, managing product lifecycle)
  • Renewable Energy (e.g. solar, wind, tidal, fuel cells, energy harvesting, nuclear, thermal, power distribution)
  • Water (e.g. Sourcing & distribution, conservation, harvesting, waste disposal, recycling)
  • Electronics (e.g. components and systems, sustainable manufacturing, automotive and industrial applications)
  • Energy Efficiency (e.g. sensing and measurement, energy saving, auto electrification & fuel economy, data centers)
  • Transportation (e.g. electric & autonomous vehicles, aviation, motors, drive controls, batteries)
  • Societal Implications / Quality of Life (e.g. global warming, sustainability education, human resources, risk-management, remediation, public policy)

HOW TO SUBMIT?

To participate in the contest students should write a 2-page (500-700-word) description (abstract) of the poster, along with authors names, respective university and contact details; and submit it using the SusTech website (include hyperlink here once weblink is created) by the specified deadline. The abstracts will be reviewed and authors notified by Sept 20th if they will be presenting at SusTech. If you have any questions or problems submitting your abstract, please contact session chairs Dr. Phani Vallabhajosyula, and Prof Michael Goryll at phani.c.v@ieee.org and michael.goryll@asu.edu. Contestants will need to prepare a poster of no larger than 48 x 36 inches and on a tri-fold board.

 

Key Dates Sept. 23, 2016 Submission deadline for poster abstract
Abstract Submission date + 2days Notification of Acceptance
Oct. 9, 2016 Final Poster Display During Conference

 PRIZES

Cash prizes will be awarded for first, second and third places as determined by the judges. First place $750; second $500; third $250. Information on the winners will be posted on the SusTech and IEEE Region 6 websites.

RULES REGARDING SUBMISSIONS

  1. Poster authors must be undergraduate or graduate students at the time of submission and may be members of a team comprising of up to four students.
  2. At least one student author must be an IEEE student member at the time of the submission of the poster to the Contest.
  3. The poster should be fully the work of the student or students and completed before they have received their engineering or scientific degree.
  4. The poster abstract should not be previously published or presented at another conference which has assigned copyright. If any plagiarism or copyright issues are found for the abstract, it will not be accepted.
  5. Poster abstracts must be submitted by the deadline. Abstracts submitted afterward will not be considered for evaluation.
  6. The organizing/review committee of the SusTech 2016 Student Poster Contest reserves the right to accept or reject any abstract without assigning any reason.

POSTER SPECIFICATIONS

  1. Posters must be tri-fold and may be no larger than 36”x48”
  2. Posters will be placed to stand alone on the tables

POSTER SESSION SCHEDULE AND SET UP FOR CONTESTANT

  1. Set up begins at 2:30 pm. At least one of the authoring students must be present at the SusTech Conference.
  2. Poster boards will be numbered.  Presenters should attach their posters to the board number corresponding to the number assigned to their poster.
  3. Judging will occur from 5:30-6:00pm.
  4. Poster session is open 3:00 pm – 7:00 pm.
  5. Take down by presenters no later than 7:10 pm.  Posters not removed by 7:10 pm will be taken to the Registration area.
  6. If selected as one of the winning posters, you will receive a ribbon on your poster and will also be notified via email.
  7. The SusTech Conference may request that prize posters be held temporarily for public display.

September 14th, 2016

The September 2016 edition of the IEEE Phoenix Section newsletter “Valley  Megaphone” is now available.  The issue includes all the information regarding IEEE-Phoenix Section and its Society Chapters. Download the PDF version from the link right here. The current and older editions of the Megaphone can always be found here.


September 8th, 2016

Tuesday, September 20th, 2016 at 5:30 PM

 On-Chip Embedded Cooling of Power and Logic Components

 Avram Bar-Cohen*, PhD – IEEE/CPMT Distinguished Lecturer

Principal Engineering Fellow, Raytheon Corporation – Sape & Airborne Systems, Rosslyn, Virginia,

abc@umd.edu

(*on Leave fromUniversity of Maryland, College Park, Maryland, USA)

 ABSTRACTieee-phoenix-section-cpmt-society-chapter-september-20

Thermal packaging technology has been a key enabler in the development of today’s microelectronic systems, including smart phones, tablet computers, back-room data-crunching supercomputers, and the navigation systems that have come to define our lives in the 21st Century. Much of the benefit that we derive from miniaturization, higher performance, lower cost and greater reliability of these quintessential 21st Century “widgets,” can be traced to improvements in thermal technology, thermal modeling, and the integration of thermal management principles and techniques into electronic product development.

A review of thermal packaging over the first 70 years of the Information Age will reveal a relentless “inward migration” of cooling technology from room ventilation and air-conditioning, to cabinet cooling, to component cooling with heat sinks and cold plates, and to today’s efforts to address on-chip hot spots and near-junction thermal transport. Attention will then be devoted to current thermal management requirements, driven by nano-electronics, which confront packaging engineers with the simultaneous “triple threat” of high-power, “hotspots,” and 3D integration in applications as diverse as high performance computing, power electronics, and RF systems. The lecture will close with a review of 3rd-generation thermal management technologies relying on intra- and interchip microfluidic cooling, use of diamond substrates, and on-chip thermoelectric coolers to implement the emerging “embedded cooling” paradigm. 

Date:           Tuesday, September 20th, 2016

Location:    Constellation Room, NXP Semiconductors, Discovery Business Center, 2108 E. Elliot Road, Tempe, Arizona..

Note New Address – Park on east side of campus – New main entrance on south side facing Elliot Road

Sign in at the security station to obtain visitor pass BEFORE 5:45 PM. Present Valid Photo ID.

You will be escorted to the meeting room. Within the building you should always be escorted..

Agenda:     5:30–6:00 PM: Social/Refreshments, 6:00–7:00 PM: Presentation, 7:00 PM: Dinner

(Pizza and Soda will be provided by the IEEE Phoenix Section CPMT Society Chapter)

IEEE members and non-members are all welcome to attend. The presentation promptly starts at 6:00 PM.