Loading Events

« All Events

  • This event has passed.

Next Generation Arithmetic for HPC and AI: An Update

September 27 @ 14:00 - 15:00

Posit arithmetic, a form of universal number (unum) computer arithmetic, was introduced at Stanford in February 2016, as a hardware-friendly drop-in replacement for floating-point arithmetic that offers higher speed, accuracy, and dynamic range using the same number of bits. Since that introduction, posits have proved their merits in machine learning and inference for Artificial Intelligence (AI) as well as PDE solvers, linear algebra, and Fourier transforms for High-Performance Computing (HPC). An open-source fast software library, SoftPosit, has been completed that is closely based on Berkeley’s SoftFloat library that allows easy and experimentally fair comparison between posits and floats. A scalable Verilog generator now exists for creating FPGA and VLSI hardware. Dozens of explorations of posit arithmetic advantages are underway at companies both large and small, and at universities around the globe. New results support the thesis that traditional floating-point arithmetic has been made obsolete by posits, and that posits, surprisingly, can also outperform fixed-point arithmetic approaches currently used for AI and signal processing.

Location:
Room: 2240
Bldg: SLA (78)
Rochester Institute of Technology
Rochester, New York
14623

Details

Date:
September 27
Time:
14:00 - 15:00
Website:
http://events.vtools.ieee.org/m/177208

Organizer

rwpeec@rit.edu