National Workshop on SoCAMMA- Supported by IEEE Communication Society
20th February 2018

IEEE Student Branch of Amrita School of Engineering, Bangalore Campus supported by IEEE Communication Society Bangalore Chapter is organizing highly skilled and demanding 2-day national workshop on

System-on-Chip Architecture for Mixed Mode Applications (SoCAMMA): with an emphasis on Field Programmability for Rapid Prototyping.

Limited seats- Register here and book your seat in advance :

Date: 23-24 March 2018

Venue: Amrita School of Engineering , Bangalore Campus, Kasavanahalli, Bangalore, 560035

Learn the Prototype Development. The Unique Opportunity !

Program Schedule  (SoCAMMA Schedule _v5)

Day 1 (23 March, Friday), 2018
08:30-09:30 Registration
9:30-10:00 Inauguration
10:00-10:45 Dr P V Ananda Mohan

VP (Retd) CDAC

Invited talk –


10:45-11:15 Tea Break
11:15-12:00 Hitesh Garg,

NXP India

“Ultra Low power Trends in Semiconductor Products and new directions for Analog Building Blocks”
12:00-12:45 Ms Swathi G

Texas Instrument

SoC Design and Testing
12:45-13:45 Lunch
13:45-16:30 Ms Vidya Vishwnathan

Amod Anandkumar,

Mathworks Inc.

Designing and Implementing Advanced Signal Processing Systems using MATLAB and Simulink with the leverage of HDL Coder™ and HDL Verifier™ to explore design choices to accelerate your FPGA and ASIC verification,
15:00-15:15 Tea Break
Day 2 (24 March, Friday), 2018
9:00-9:45 Prof Subajit Sen

IIIT Bangalore

Digitally Assisted Analog & Mixed Signal Design








Dr Ganesan Thiagrajan




Dr Javed GS

Terminus Circuits Pvt Ltd

Embedded RF Design




SerDes Design

11:45-12:40 Dr. Pratap Kumar Das,

Achronix Semiconductor Corp

Embedded FPGA
12:40-13:45 Lunch
13:45-17:00 Mr. Rajesh et. al.,

Oppila Microsystems


Demo on Anadigm’s FPAA (Field Programmable Analog Array)
15:30-16:00 Tea Break



Learn the Prototype Development. The Unique Opportunity !