DevIC-2017 Call For Papers

 logo2_web

Call for Papers

DevIC 2017 invites original papers in the research areas of various aspects of modeling and simulation of nanomaterials, structures and devices, their analysis and implementation in digital and analog circuits. Articles announcing significant and original results are highly solicited.

Publication

INSTRUCTIONS FOR SUBMISSION OF PAPERS FOR EVALUATION:

Papers  should  be           typeset                by           using     the         general typesetting         instructions available      at: www.ieee.org/conferences_events/conferences/publishing/templates.html. Also the author shall submit an undertaking that the paper submitted is the original work of the author(s) and the paper is not submitted or published in any other conferences/journals.

Authors of accepted papers will receive more specific typesetting instructions later. Submissions must be in either MS doc or pdf formats. The size of the paper must be within 5 pages

(the number of pages include all figures, tables, and references). The first page of the paper should include the followings:

  • Title of the paper
  • Name, affiliation, postal address, and email address of each author (identify the name of the Contact Author)
  • Abstract (between 100 and 120 words)
  • A maximum of 5 topical keywords that would best represent the work described in the
  • Write the type of the submission as “Full/Regular Research Paper”
  • Write the name of this conference (i.e., 2017 Devices for Integrated Circuit).
  • The actual text of the paper can start from the first page (space permitting).

 

IEEE PDF eXpress: A freely available online tool designed to assist conference authors in complying with the IEEE PDF requirements
http://www.ieee.org/web/publications/pubservices/confpub/pdfexpress.html

 

Electronic Submission link through EasyChair:
https://easychair.org/conferences/?conf=devic2017

 

Important Dates:

Call for Paper: September 1, 2016

Paper submission deadline: December 1, 2016  December 31, 2016 January 15, 2017  Paper submission closed

Author notification after 1st round of review: January 15, 2017 January 20, 2017  January 31, 2017

Date of re-submission of revised manuscript: February 10, 2017

Last date of the Notification of final acceptance: February 15, 2017

Last date for payment of Registration Fee: 10 days from the date of final acceptance

Camera-ready paper deadline: March 01, 2017

 

Topics of interest

Papers are solicited across the general field of electronic devices. Topics of interest include, but are not limited to:

  • CMOS Processes, Devices and Integration:
    CMOS scaling; Silicon Nanowires;Simulation of Dual gate, Vertical Channel and Cylindrical Gate MOSFET/OTFTs;Advanced Memory Devices; Novel MOS device architectures;
  • Emerging Non-CMOS Devices & Technologies:
    Emerging Electronic Device Materials (graphene, MoS2, etc.); Magnetic Devices;Novel MOS device architectures; III-V, and 2D Electronic Devices; New high-mobility channels (strained Si, Ge, SiGe);Nano-electro-mechanical Devices and Systems;High frequency digital and analog devices including THz; Novel non-CMOS materials, processes and devices, (nanotubes, nanowires and nanoparticles, including carbon, graphene, metal oxides, …) for electronic, optoelectronic, sensor & actuator applications;
  • Device Modelling & Simulation: Modeling and simulation of nanomaterials, structures, and devices; Modelling of Solid State Devices;Modelling and Simulation of FinFETs, MOSFETs, CMOS, Tunnel-FETs; Oxide Thin Film Transistors; Organic Thin Film Transistors (OTFTs); Modelling and Simulation Organic Novel Device Structures; Physics and Modeling of Submicron and Nanoscale Microelectronic and Optoelectronic Devices Including Processing, Measurement, and Performance evaluation; Analytical Models for Organic Devices;Modelling and Simulation of Organic Light Emitting Diodes (OLEDs); Modelling and Simulation of Organic Solar Cells;Mathematical Models of Novel Electronic Device Structures
  • Device Characterization, Reliability & Yield: Front-end and back-end manufacturing processes; 3D integration and wafer-level packaging; Reliability of materials, processes and devices; Advanced interconnects; ESD, latch-up, soft errors, noise and mismatch behavior, hot carrier effects, bias temperature instabilities, and EMI; Defect monitoring and control; Metrology; Optimization of Device Performance Parameters;Terahertz Devices;Wide-bandgap Devices;Semiconductor Process Technologies;Nanostructures and devices for biomedical applications;Photovoltaics and Sensors System Design; 3D Systems and Packaging Technologies; Nanostructures for future generation solar cells;
  • Devices with New material systems:
    Graphene and carbon nanotubes based materials and devices;Biological Devices; Organic/Polymer Electronics; Novel Optoelectronic Devices
  • Devices for Low power applications:
    Energy Scavenging Devices; Materials and devices for energy and environmental applications;
  • Low dimensional devices:
    Low dimensional Semiconductors: Growth & Applications;Quantum Devices;Quantum effect in Nanoscale Electronic and Optoelectronic Devices;Spin-based Devices;Computational Modeling at the Nanoscale;Fundamental and applications of nanotubes, nanowires, quantum dots and other low dimensional materials;
  • Design and Simulation of Circuits with nanoscale devices:
    Modelling and Simulation of Novel Circuits;Modelling of Circuit Networks, Analogue and Digital Circuits; Mixed Mode Circuit Simulations; Applications of Numerical Methods to the Modeling and Simulation of Devices and Processes; Modelling and Simulations Device Circuit Co-design
  • MEMS, Sensors & Display Technologies:Smart Monitoring and metering such as Design, fabrication, modeling, reliability, packaging and smart systems integration of actuators (discrete SoC, SiP, or heterogenous 3D integration); MEMS, NEMS, optical, chemical or biological sensors; Display technologies; High-speed imagers; TFTs; Organic and flexible substrate electronics.
  • Advanced & Emerging Memories: Novel memory cell concepts and architectures; Embedded and stand-alone memories; DRAM, FeRAM, MRAM, PCRAM, CBRAM, Flash, SONOS, nanocrystal memories; single and few electron memories; 3D systems integration; Organic memories; NEMS-based devices.
  • High frequency wireless communication:
    Devices/circuits/systems used in Microwave & Antenna Technologies, Communication Systems & Signal Processing, Cognitive Radio & Cooperative Systems, New Communication Paradigms with their Hardware Architectures & Implementation such as Microwave Integrated Circuit, radio frequency, microwave, millimetre-wave, and terahertz devices, systems, and technologies, high-frequency related topics, from materials and technologies to integrated circuits and systems, their aspects:theory, simulation, design, measurement, and real-world applications, filters and passive components, modelling and design of RF MEMS, high-frequency and high data-rate microwave photonics, highly stable and ultra low-noise signal sources, linearisation techniques, emerging materials and technologies for microwave components such as metamaterials, nanotechnologies, tunable and reconfigurable RF components and systems, and system-in-package solutions, mobile terrestrial and satellite-based communications, advanced radar sensing and imaging, navigation and localization, process automation, automotive and intelligent traffic systems, energy harvesting and wireless power transfer, high-power applications, biomedical sensing, and electromagnetic compatibility issues.

TYPE OF SUBMISSIONS:

Only Full/Regular Research  Papers  (Strictly  within  5  pages):Regular  Research  Papers  should provide detail original research contributions. They must report new research results that represent a contribution to the field; sufficient details and support for the results and conclusions should be provided. The works presented in regular papers are expected to be at a stage of maturity that with some additional work can be published as journal papers. The authors are requested not to prefix their credentials i.e. Dr., Prof., HOD, Ms, Mrs, Scholar, etc. in authors name.

COPYRIGHT INFORMATION:

IEEE policy requires that prior to publication, all authors or their employers must transfer to the IEEE in writing any copyright they hold for their individual papers. Please visit the following URL to learn more about securing copyright transfer www.ieee.org/web/publications/rights/copyrightmain

The signed and scanned (in pdf only) IEEE copyright form must be accompanied with the final camera-ready paper. Download the Copyright form in (.pdf) .

Review Process:

After submission, the paper enters into the review process. DevIC 2017 research papers are reviewed using a single-blind process managed through EasyChair. A committee of reviewers selected by the Technical Committee will review the documents and rate them according to quality, relevance, correctness, and originality. The review process of research papers (full papers and short papers) for DevIC 2017 will be a two-round process.

Papers are reviewed on the basis that they do not contain plagiarised material and have not been submitted to any other conference at the same time (double submission).

Follow these links to learn more:

IEEE Policy on Plagiarism

IEEE Policy on Double Submission

IEEE Paper Review Process

Papers may be submitted to a plagiarism checker service (Viper) in order to check the originality of its contents.

In the first round, papers are reviewed independently by a minimum of three members of the conference Technical Program Committee (TPC). No outside reviewing is used for DevIC 2017. Following the abstract submission deadline, program committee members are asked to bid on potential papers of interest based on their titles and abstracts alone. These expressed preferences are then used to assign papers to reviewers once the final submission deadline has passed. This process is used in an effort to best match papers topics with reviewer expertise. Assigned reviewers submit their anonymous reviews through EasyChair.

Based on the review, a decision will be made as to whether a paper will be invited to “revise & resubmit” or will be rejected. Rejected papers cannot be resubmitted to DevIC 2017, but can be submitted to other venues. Papers invited to revise and resubmit will have Ten days time after notification before submitting to the EasyChair system again. Reviews will make explicit how the reviewers think a paper could be improved. Deadline for re-submissions is March 15, 2017. Re-submissions must include a ‘summary of changes’ that details how the authors have responded to the reviews and improved their paper. In the second round, each of the resubmitted papers will be reviewed again by the same three reviewers and decisions on acceptance or not will be made. Please note that an invitation to “revise & resubmit” does not guarantee acceptance, and the final decision will be made on the basis of the revised paper only.

The “revise & resubmit” review process gives authors a chance to improve their paper very much like when submitting to a journal, though with strict deadlines. Thus it is an opportunity to improve papers on matters that in a single review process might be a cause for rejection such as grammar, missing references, need for clarity of method or analysis, lack of explicitly relating the work to relevant previous studies or the field of participatory design. It is also an opportunity for authors of papers that might have been accepted in a single round process to further strengthen their paper. With two rounds of reviews and the ‘summary of changes’ letter communication between authors and reviewers will be strengthened. Authors will be notified of the final decisions along with the comments via email no later than the notification date listed in the Call For Papers.

DevIC 2017 Conference Committee

DevIC 2017 Home Page

DevIC 2017 Registration

DevIC 2017 Plenary Talk