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Date: May 10th, 2016
Package Requirements for High-Speed Systems



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Upcoming Events

The following schedule and location hold for most events, unless otherwise noted:

  • 6:30pm: Networking/Light Dinner
  • 7:00pm: Announcement
  • 7:05pm: Presentation
  • 8:15pm: Adjourn

Cost: Free. Food donation accepted: $2 for IEEE member, $5 for non-IEEE member.

Location: QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA

We would appreciate suggestions for speakers to present at our meetings in the future.

Package Requirements for High-Speed Systems

Date: May 10th, 2016

IEEE SCV CAS is proudly co-sponsoring IEEE/CPMT Lunch Meeting, in the Santa Clara Valley:

    Package Requirements for High-Speed Systems
— Dr. Wendem T. Beyene, Rambus Inc.

Tuesday, May 10, 2016

  • Optional lunch provided ($10 for non-members, $5 for IEEE members/students/unemployed)
  • Registration (and sandwiches/drinks) at 11:30 AM
  • Presentation-only (no cost) at 12:00 PM noon (come at 11:45 AM)
  • Please reserve by the end of May 8, so we can provide the food.
  • We welcome those looking for employment to bring copies of your resume with you. We will have a table set up for you to sit and network with others.


Please register in advance for this event, using our CPMT Chapter’s EventBrite registration site.

You may register yourself, plus others from your company/institution, for this lunch and presentation. Please make anon-line payment for the lunch.

LOCATION: Texas Instruments Building E Conference Center
2900 Semiconductor Dr. (off Kifer Rd), Santa Clara — click map at right.

    As data rates increase rapidly in high speed systems — such as in SerDes and memory systems — to meet the bandwidth growth required by various applications, the electrical performance of packages has become critical. In addition, the role of new emerging 2.5D and 3D IC packaging platforms with ever-increasing system integration requirements have made the role of packaging even more important. The sources of signal loss, noise coupling and discontinuities in packages must be fully understood and minimized when designing packages. At the same time, the design and development of packages have to meet cost, performance, form factor and reliability goals. In this talk we will examine the key electrical characteristics: signal loss, signal crosstalk, return loss, mode conversion, power integrity and other important factors affecting the bandwidth of high-speed systems. These key performance metrics are discussed using measurement results from various package designs.

Speaker Biography:
    Wendem T. Beyene received his B.S. and M.S. degrees in Electrical Engineering from Columbia University, in 1988 and 1991 respectively, and his Ph.D. degree in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign, in 1997. In the past, he was employed by IBM, Hewlett-Packard, and Agilent Technologies. He is currently a technical director at Rambus Inc. where he is responsible for signal and power integrity of multi-gigabit serial and parallel interfaces.

Tutorial on Selected Topics in RF, Analog and Mixed Signal Circuits and Systems

Date: July 20th, 2016

 (Jointly sponsored by IEEE CAS and IEEE SSC Societies and organized by IEEE SCV SSCS and IEEE SCV CAS)

Program Chairs: Dr. Kiran Gunnam and Dr. Vahidfar Vahid

Event Logistics:  Keplin Johansen, Chair, SCS SCV Chapter and Lizhen Zheng, Chair CAS SCV Chapter

For registration questions, please contact through registration site contact email. Please register in advance through our IEEE meeting registration website.   The online registration deadline is noon, July 18th, 2016.

Venue: TI auditorium, Santa Clara

Texas Instruments Silicon Valley Auditorium 2900 Semiconductor Dr., Santa Clara, CA 95051 Directions and Map


July 20th

Selected Topics, Part I

(each talk is 1 hour followed by 15 minutes of Q&A)

4pm-4.30pm-Sign-in, pizza, brief Introduction of speakers

4.30pm-5.45pm- Prof. Tom Lee, “Oscillator Phase Noise”

6.00pm-7.15pm- Dr. Nikola Nedovic, Clock and Data Recovery in High-Speed Wireline Communication

7.30pm-8.45pm- Dr. Bhupendra Ahuja, PLLs

8.45pm-9.00pm- event wrap up


July 21st

Selected Topics, Part II

4pm-4.30pm-Sign-in, pizza, brief Introduction of speakers

4.30pm-5.45pm- Dr. Osama Shana’a, CMOS Digital RF transmitters

6.00pm-7.15pm- Prof.Boris Murmann,“Equalization and A/D conversion for high-speed links”

7.30pm-8.45pm- Dr. Alireza Shirvani, RF CMOS Power Amplifiers

8.45pm-9.00pm- event wrap up


Course slides will be delivered to registered attendees as e-book 2 days before the course and will be also available on SSCS and CAS websites for the society members.


Event Pricing:

Regular Attendees: $100 (both days); $70 (for any one of the day)

TI attendees: $25 (both days); $15 (for any one of the day)  (to cover the cost of the food); TI company email address is required for registration, check badge at admission.

IEEE members: 10% discount; please sign in with your IEEE web account during the registration to get the discount.

Refund policy: Cancellation has to be requested online by July 15, 9pm. Refund of the original fee minus handling fee $5 will be made by check.

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