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Date: September 25th, 2019
Educational Seminar: Control for Power Electronics (Co-sponsored Event)



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Upcoming Events

The following schedule and location hold for most events, unless otherwise noted:

  • 6:30pm: Networking/Light Dinner
  • 7:00pm: Announcement
  • 7:05pm: Presentation
  • 8:15pm: Adjourn

Cost: Free. Food donation accepted: $2 for IEEE member, $5 for non-IEEE member.

Location: Cypress Semiconductor Corporation, Main Auditorium in Building 6, 198 Champion Ct, San Jose, CA 95134

We would appreciate suggestions for speakers to present at our meetings in the future.

Instructions for attending live broadcast events using the Zoom conference systems

Educational Seminar: Control for Power Electronics (Co-sponsored Event)

Date: September 25th, 2019

Event organized by Power Electronics Society (PELS)

Time: 1:00pm to 5:30pm
Location: Texas Instruments, Building E Auditorium, 2900 Semiconductor Dr, Santa Clara, CA 95051

Pre-registration Required:
General Attendees: $80, IEEE Members: $60, PELS and CASS members: $50
Students and TI-ers: FREE (Limit 10 each)
All on-site registrations will be $100

1:10pm to 2:00pm: Introduction to Control Loops
Abstract: This talk starts out easy on the several simple control methods for a switching power supply. It covers
fixed frequency for both voltage modes and current mode control. Showing how adding in just the right
amount of extra ramp help stabilize the output for >50% duty cycles. Variable frequency control methods like
Constant ON Time and a few of its variations are covered. To be able to shape the gain and keep it stable, we
will cover the error amp and its compensation, covering Type1, Type 2, Type 2B, and Type 3 compensation.
The examples used for this seminar use in the buck regulator.
Bio: Prabal Upadhyaya was born in Kathmandu, Nepal, in 1979. He received the M.S. degree in electrical
engineering from University of Idaho. Currently, he is a principal application engineer at Alpha and Omega
Semiconductor, Inc. Previously he has held various positions at ROHM semiconductor, Intersil corporation
(since acquired by Renesas Electronics) and Cypress semiconductor.

2:00pm to 2:50pm: A Dive into Fixed Frequency and Constant ON-Time Control Architectures for
Power Converters
Abstract: Throughout the years various control architectures have been adopted by power engineers in order to
regulate the constant output voltage. Fixed frequency control techniques have dominated the market as the
workhorse for precise control under most load conditions. However, the demand for longer battery life and
improvements in efficiency at light loads creates a window of opportunity for hysteretic control and various
power saving control techniques. In this presentation, details on voltage mode, current mode and constant
On-Time architectures will be explained. Pros and cons for each architecture will be discussed along with
practical issues with feedback loop design, effect of parasitic elements and loop gain measurement.
Bio: Nassif Abijaoude is an applications engineer at On Semiconductor developing DC-DC products in the telecom
and consumer space. Prior to his recent work in the telecom market, he helped develop DC-DC products for the
computing sector. Nassif obtained his Bachelor of Science degree in Electrical Engineering from California
Polytechnic State University (SLO) in 2010. He also holds a Master’s Degree In Electrical Engineering from San
Jose State University.

3:00pm to 3:30pm: Break and Refreshments

3:30pm to 4:20pm: Multiphase Converters: Higher Powers, Lower Ripple, Faster Response
Abstract: Multiphase converters deliver more power to the load, but also increase performance by interleaving the
switching waveforms to lower ripple voltage. With more switching events, multiphase converters have more
opportunity to respond to fast transients, typical in microprocessor systems. This talk will introduce
multiphase buck converters, discuss popular control strategies, and address methods of current balance, a
typical challenge with these converters.
Bio: Doug Osterhout has worked in power electronics for over 20 years. He started at Celestica Power Systems
designing kilowatt ac-dc power supplies. In 2001, he switched industries to semiconductors where’s held various
positions at Micrel, ADI, and ON Semi. There he designed LED drivers, Intel CPU power, and offline converters.
For the last 2 years, Doug has been at Google working on consumer products.

4:20pm to 5:10pm: From OpAmps to MCU’s: Intro to Digital Control
Abstract: Learn how to transition from op-amp and comparator-based controller to digital microcontroller power
controllers. Digital control provides unique flexibility to tune the converter setpoints and parameters as a
function of load or any digital input. However, moving to digital control introduces its own set of challenges.
This talk will discuss the advantages of digital control, what to look for when selecting a microcontroller for
power, and how to translate continuous-time controllers into discrete-time digital controllers. Finally,
common pitfalls when implementing digital control will be discussed.
Bio: Dr. Michael Seeman is President and Founder of Eta One Power, Inc. Eta One Power develops advanced
simulation and optimization software focusing on increasing power density and efficiency of power supplies. He
has 15 years of experience in cutting-edge power conversion solutions using wide-bandgap technologies and
resonant converter architectures. He previously worked at Texas Instruments and two power electronics
startups in Silicon Valley. Michael received his S.B. from MIT and M.S. and Ph.D. from UC Berkeley. He is an IEEE
member and chair of the SF Bay Area PELS chapter.

4:20pm to 5:10pm: Q&A and Wrap-up

CASS Distinguished Lecturer Event with Dr. Shanti Pavan: “Dissecting Design Choices in Continuous-time Delta-Sigma Converters”

Date: September 26th, 2019

CASS Distinguished Lecturer Event with Dr. Shanti Pavan:

“Dissecting Design Choices in Continuous-time Delta-Sigma Converters”

Event sponsored and organized by:

Circuits and Systems Society – Santa Clara Valley Chapter (CASS-SCV)



Thursday, September 26th, 2019. 6 PM – 8 PM


6:00 – 6:30 PM Check-in / Networking & Refreshments

6:30 – 7:30 PM Lecture

7:30 – 7:45 PM Q&A

7:45 PM Adjourn

Lecture will be broadcast on Zoom and recorded. Please register to receive Zoom conference details.


UC Silicon Valley Campus

3290 Scott Blvd, Santa Clara, CA 95054

Registration Link:



TITLE: Dissecting Design Choices in Continuous-time Delta-Sigma Converters


Continuous-time Delta-Sigma Modulators (CTDSMs) are a compelling choice for the design of high resolution analog-to-digital converters. Many delta-sigma architectures have been published (and continue to be invented). This leaves the designer with a bewildering array of choices, many of which seem to pull in opposite directions. Further, it is often difficult to make a clear comparison of various architectures, as they have been designed for dissimilar specifications, by different design groups, and in different technology nodes. This talk examines various alternatives for the design of power efficient single-loop continuous-time delta sigma converters.


Shanthi Pavan received the B.Tech from IIT Madras in 1995 and the doctoral degree from Columbia University, New York City, in 1999. He is currently a Professor of Electrical Engineering at IIT Madras. His research interests are in the areas of high speed analog circuit design and signal processing.

He is a recipient of many awards, including the IEEE Circuits and Systems Society Darlington Best Paper Award (2009) , the Swarna Jayanthi Fellowship (2009) and the Shanti Swarup Bhatnagar Award (2012). He has served as the Editor-in-Chief of the IEEE Transactions on CIrcuits and Systems:Regular Papers. He has served on the Technical Program Committee at the International Solid State Circuits Conference (ISSCC), and as a Distinguished Lecturer of the Solid-State Circuits Society. He is currently a distinguished lecturer of the IEEE Circuits and Systems Society. He is a fellow of the Indian National Academy of Engineering (INAE) and the Institute of Electrical and Electronic Engineers (IEEE). He is the coauthor (with Richard Schreier and Gabor Temes) of “Understanding Delta Sigma Converters”, published by the Wiley-IEEE Press.

“Millimeter-Wave Power Amplifiers In FinFET Technology”

Date: October 16th, 2019

“Millimeter-Wave Power Amplifiers In FinFET Technology”

Dr. Christopher Hull, Senior Principal Engineer & Director: Radio Circuit & Technologies, Intel Labs

Event Organized By:

Circuits and Systems Society (CASS) of the IEEE Santa Clara Valley Section



6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Lecture will be broadcast on Zoom and recording will be available. Please register to receive zoom conference details before the event.

Registration Link: Here


Fifth generation cellular communications standards (5G) target Gb/s data-rates, pushing the industry beyond to use frequencies above 26 GHz. To maintain acceptable link budgets with sufficient antenna apertures, arrays are typically required at these frequencies and electrical beam steering is needed to retain spatial coverage. CMOS FINFET’s represent an ideal technology match, given the high level of integration required; however, power amplifier design is challenging in this technology. Fortunately, due to the array gain and distributed power among many power amplifiers, the power output required per PA is moderate. This talk will focus on how to design such power amplifiers in FINFET technologies suitable for high levels of integration on a multi-transceiver die.


Christopher Hull received his PhD from the University of California, Berkeley, in 1992. He joined Rockwell Semiconductor Systems in Newport Beach, CA in 1992. In 1998 Chris joined Silicon Wave in San Diego, California, In 2001, Chris joined Innocomm Wireless, which was subsequently acquired by National Semiconductor. . In May, 2003 Chris joined the Wireless Networking Group of Intel, in San Diego, California. And In June 2005, Chris moved to Hillsboro Oregon. In 2013, Chris spent1 year on international assignment in Munich, Germany to work closely with his colleagues from Intel Mobile Communications on 4G cellular transceivers. Since May 2015, Chris has been working as Director/Sr. Principal Engineer for Intel Labs.


QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA 95051

Live Broadcast:

Lecture will be broadcast on Zoom and recording will be available. Please register to receive zoom conference details before the event.

Admission Fee:

All admissions free. Suggested donations to cover food and water:

Non-IEEE: $5, Students (non-IEEE): $3, IEEE Members (not members of CASS or SSCS): $3

Online registration is recommended to guarantee seating.

[] Machine Learning and Deep Learning Boot Camp

Date: October 17th, 2019

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August 29th through October 17th, 2019,; Machine Learning and Deep Learning Boot Camp, @Z-Park, 4500 Great America Pkwy, Santa Clara

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