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Date: June 27th, 2018
Neuromorphic Chips: Addressing the Nanotransistor Challenge by Combining Analog Computation with Digital Communication by Dr. Kwabena Boahen

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Upcoming Events

The following schedule and location hold for most events, unless otherwise noted:

  • 6:30pm: Networking/Light Dinner
  • 7:00pm: Announcement
  • 7:05pm: Presentation
  • 8:15pm: Adjourn

Cost: Free. Food donation accepted: $2 for IEEE member, $5 for non-IEEE member.

Location: QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA

We would appreciate suggestions for speakers to present at our meetings in the future.

Neuromorphic Chips: Addressing the Nanotransistor Challenge by Combining Analog Computation with Digital Communication by Dr. Kwabena Boahen

Date: June 27th, 2018

DESCRIPTION

PROGRAM

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:30 PM Talk
7:30 – 8:00 PM Q&A

Speaker:

Kwabena Boahen, Professor of Bioengineering and Electrical Engineering, Stanford University

Abstract:

As transistors shrink to nanoscale dimensions, trapped electrons–blocking “lanes” of electron traffic–are making it difficult for digital computers to work. In stark contrast, the brain works fine with single-lane nanoscale devices that are intermittently blocked (ion channels). Conjecturing that it achieves error-tolerance by combining analog dendritic computation with digital axonal communication, neuromorphic engineers (neuromorphs) began emulating dendrites with subthreshold analog circuits and axons with asynchronous digital circuits in the mid-1980s. Three decades in, they achieved a consequential scale with Neurogrid, the first neuromorphic system with billions of synaptic connections. Neuromorphs then tackled the challenge of mapping arbitrary computations onto neuromorphic chips in a manner robust to lanes intermittently–or even permanently–blocked by trapped electrons. Having demonstrated scalability and programmability, they now seek to encode continuous signals with spike trains in a manner that promises greater energy efficiency than all-analog or all-digital computing across a five-decade precision range.

About the Speaker:

Kwabena Boahen is a Professor of Bioengineering and Electrical Engineering at Stanford University, where he directs the Brains in Silicon Lab. He is a neuromorphic engineer who is using silicon integrated circuits to emulate the way neurons compute, and linking the seemingly disparate fields of electronics and computer science with neurobiology and medicine. His lab developed Neurogrid, a specialized hardware platform created at Stanford that enables the cortex’s inner workings to be simulated in real time–something outside the reach of even the fastest supercomputers. His interest in neural nets developed soon after he left his native Ghana to pursue undergraduate studies in Electrical and Computer Engineering at Johns Hopkins University, Baltimore, in 1985. He went on to earn a doctorate in Computation and Neural Systems at the California Institute of Technology in 1997. From 1997 to 2005 he was on the faculty of University of Pennsylvania, Philadelphia PA. With over ninety publications to his name, including a cover story in the May 2005 issue of Scientific American, his scholarship has been recognized by several distinguished honors, including the National Institute of Health Director’s Pioneer Award in 2006. In 2016, he was named a fellow of the Institute of Electrical and Electronic Engineers and of the American Institute for Medical and Biological Engineering. His 2007 TED talk, A Computer that Works like the Brain, has been viewed over half-a-million times.

Admission Fee:

Open to all to attend
(Online registration is needed. If you did not register, seating is not guaranteed.)

  • IEEE CIS members – free
  • Students – $3 (Register at Door $3)
  • IEEE (non-CIS) members – $7 (Register at Door $10)
  • Non-members – $10 (Register at Door $15)

You do not need to be an IEEE member to attend!

Eventbrite Link:

https://www.eventbrite.com/e/neuromorphic-chips-addressing-the-nanotransistor-challenge-by-combining-analog-computation-with-tickets-46793509647?aff=ebdssbdestsearch


Distinguished Lecturer Seminar by Prof. Gabor C. Temes: “A 13b ENOB Noise-Shaping SAR ADC with a Two-Capacitor DAC”

Date: July 26th, 2018

DESCRIPTION

“A 13b ENOB Noise-Shaping SAR ADC with a Two-Capacitor DAC”

Prof. Gabor C. Temes, School of EECS, Oregon State University

IEEE Santa Clara Valley Section

Eventbrite Registration Link

PROGRAM

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Abstract:

An active noise-shaping successive-approximation-register (SAR) analog-to-digital converter is described. Instead of binary-weighted capacitors, it uses two equal-valued capacitors as the embedded digital-to-analog converter (DAC). Thus, the capacitance spread in the DAC is much smaller than that of the conventional binary-weighted capacitor array, and the mismatcherror can be greatly reduced. The circuit provides first-order noise shaping, which can improve the ADC’s linearity even for a small oversampling ratio. Also, the proposed architecture uses a monotonic approximation procedure, which requires fewer conversion steps than for a conventional SAR ADCs. The ADC was fabricated in 0.18 um CMOS technology. For a 2 kHz signal bandwidth, it achieved a 78.8 dB SNDR. It consumes 74.2 mW power from a 1.5 V power supply. The performance can be drastically improved by introducing noise mitigation schemes and higher-order noise shaping.

Bio:

Gabor C. Temes received the Ph.D. degree in Electrical Engineering from the University of Ottawa, ON, Canada, in 1961, and an honorary doctorate from the Technical University of Budapest, Budapest, Hungary, in 1991.

He held academic positions at the Technical University of Budapest, Stanford University and the University of California at Los Angeles. He worked in industry at Northern Electric R&D Laboratories and at Ampex Corp. He is now a Professor in the School of Electrical Engineering and Computer Science at Oregon State University.

Dr. Temes received the IEEE Graduate Teaching Award in 1998, and the IEEE Millennium Medal in 2000. He was the 2006 recipient of the IEEE Gustav Robert Kirchhoff Award, and the 2009 IEEE CAS Mac Valkenburg Award. He received the 2017 Semiconductor Industry Association-SRC University Researcher Award. He is a member of the National Academy of Engineering.

Venue:

QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA 95051

Admission Fee:

Open to all to attend
Online registration is recommended to guarantee seating.

You do not need to be an IEEE member to attend!

 


Lecture by Dr. Mihai Banu: “Massive MIMO Active Antenna Arrays for Advanced Wireless Communications”

Date: August 9th, 2018

DESCRIPTION

“Massive MIMO Active Antenna Arrays for Advanced Wireless Communications”

Dr. Mihai Banu, CTO, Blue Danube Systems, Santa Clara CA

IEEE Santa Clara Valley Section

Eventbrite Registration Link

PROGRAM

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Abstract:

Recently, many experts in academia and industry have been strongly advocating the concept of Massive MIMO for application in 4G and 5G systems. While the push for larger base station antenna aperture is probably the right idea for many systems, there are important subtleties in the Massive MIMO concept, which make its practical application far from straightforward. These include HW complexity, channel estimation challenges, signal coherency issues, radio chain to antenna mapping, and multi-band designs. This talk will discuss the main types of Massive MIMO systems pointing out their benefits and limitations for various RAN systems and frequency bands. This talk will also present field trial results for Blue Danube Massive MIMO products operating in mid-band spectrum.

Bio:

Dr. Banu has over 30 years experience in circuits and systems R&D, with emphasis on analog, radio frequency and mixed-signal integrated circuits.

His experience encompasses many areas from invention and demonstration of new circuits and system concepts, to design methodologies and product development.

Dr. Banu is Founder of Blue Danube Systems, which received Series A venture capital funding and started operations in 2013. He developed the Blue Danube Systems technology concepts at MHI Consulting, a small consulting firm founded and owned by Dr. Banu since 2006. Prior to that, he was R&D director at Agere Systems, working on analog circuits, RF systems for wireless LANs and wireless circuits research.

From 1995 to 2000, Dr. Banu was Head of the Communications Circuits Research department at Lucent Technologies, where he was responsible for advanced work in circuit design and Si technology process-device enhancements including SiGe BiCMOS. From 1980 to 1995, he was a Member of Technical Staff at AT&T Bell Laboratories in the Communications Sciences Division, the Physical Sciences Division and the VLSI Research Department.

Dr. Banu is author of more than 30 technical papers, several book chapters and many U.S. and international patents. As a recognized IC design expert, he was invited to contribute in many panels and workshops at major international conferences, as well as teach short courses.

He received his bachelor’s, master’s, and Ph.D. degrees in electrical engineering from Columbia University and he is an IEEE Fellow.

Venue:

QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA 95051

Admission Fee:

Open to all to attend
Online registration is recommended to guarantee seating.

You do not need to be an IEEE member to attend!



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