Location: QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA

Time: 6:30pm-8:15pm

Registration Cost: Free. Click Here to Register. Food donation accepted: $2 for IEEE member, $5 for non-IEEE member

Speaker: Dr. Xiang Gao, Marvell

Abstract  This is a review talk of the sub-sampling PLL technique. It will cover the development of the sub-sampling PLL architecture and its applications. This talked is based on the speaker’s IEEE Custom Integrated Circuits Conference (CICC) 2015 invited review paper.

Bio  Xiang Gao received the M.Sc. and Ph.D. degree in EE with cum laude from the University of Twente, The Netherlands, in 2006 and 2010 respectively. Since 2010, he has been with Marvell, Santa Clara, CA, working on RF and analog IC design for wireless communication systems. He is currently a design manager at Marvell and a TPC member of ISSCC and RFIC.

Presentation available in pdf