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Date: September 21st, 2018
IEEE Circuits and Systems Society-Silicon Valley (CAS-SV) Artificial Intelligent For Industry Forum



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Events on May, 2017

“Energy Efficient memory design for the compute continuum and beyond” by Dr. Jaydeep Kulkarni, Staff Research Scientist at Intel Corporation

Date: May 22nd, 2017

IEEE SCV CAS proudly sponsors the upcoming technical talk on Monday, May 22, 2017 by Dr. Jaydeep Kulkarni, Staff Research Scientist at Intel Corporation with the title of

“Energy Efficient memory design for the compute continuum and beyond” 



With the rapid advances in computing systems spanning from billions of IoTs (Internet of Things) to high performance exascale supercomputers, energy efficient design is an absolute must. Moreover, with the emergence of neural network accelerators for machine learning applications, there is a growing need for large capacity memories. It is estimated that by 2040, around 1 Trillion internet connected devices will be deployed generating millions of Zettabytes (1 Zetta = 10 21 ) consuming tens of Zetta-joules of compute energy/year. These trends clearly indicate the paramount importance of energy efficient memories across the compute continuum and to cater storage needs for future workloads.

In this seminar, I will discuss the circuit solutions for realizing energy efficient memory arrays. Supply voltage scaling is the primary driver to reduce energy consumption. The minimum operating supply voltage (Vmin) of a compute block consisting of static CMOS datapath logic and memory arrays is typically limited by process variations in the memory bitcells using minimum sized transistors. I will present an overview of low power memory design using novel bitcell topologies, Vmin-assist techniques, high density array designs, and adaptive and resilient design for reducing V/F guardbands.

I will conclude the seminar with by highlighting the importance of memories on the next generation computing systems and how cross-layer interactions across the hardware stack harnessing the benefits of each of its components are required to realize future energy efficient systems for the data centric world.

Bio for Dr. Jaydeep Kulkarni:

Dr. Jaydeep Kulkarni is a Staff Research Scientist at Intel Corporation. He received the Bachelor of Engineering (B.E.) degree from the University of Pune, India in 2002, the Master of Technology (M. Tech.) degree from the Indian Institute of Science (IISc) Bangalore, India in 2004 and Ph.D. degree from Purdue University, West Lafayette, IN, in 2009 all in electrical engineering. During 2004-05, he worked as a Design Engineer at Cypress Semiconductors, Bangalore and designed I/O circuits for micro-power SRAMs. He joined Circuit Research Lab (CRL) at Intel Corporation, Hillsboro, OR in 2009, where he is currently working as a staff research scientist. His research is focused on energy efficient integrated circuits and systems, emerging nanotechnologies, and alternative computing models. He has filed 30 patents, published 2 book chapters and 55 papers in referred journals and conferences.

Dr. Kulkarni received 2004 best graduate student award from IISc Bangalore, two Semiconductor Research Corporation’s (SRC) inventor recognition awards, 2008 ISLPED design contest award, 2008 Intel foundation Ph.D. fellowship award, 2008 SRC TECHCON best paper in session award, 2010 Purdue school of ECE outstanding doctoral dissertation award, three Intel patent recognition awards, seven Intel divisional recognition awards for successful technology transfers, 2015 IEEE Transactions on VLSI systems best paper award, and 2015 SRC outstanding industrial liaison award. He has participated in technical program committees of A-SSCC, ISLPED, ISCAS, and ASQED conferences. He is serving as a technical program co-chair for 2017 ISLPED, an associate editor for IEEE Transactions on VLSI Systems, and as an industrial liaison for SRC, NSF, Stanford System-X alliance, Stanford-NMTRI and STARnet research programs. He is a senior member of IEEE.


6:30pm: Networking/Light Dinner
7:00pm: Announcement
7:05pm: Presentation
8:15pm: Adjourn

Where: Qualcomm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA 95051

Registration Link:

Registration Cost: Free. Food donation accepted: $2 for IEEE member, $5 for non-IEEE member



“Time-Based Circuits – not just the Single Slope!” by Dr. Matt Straayer from Maxim Integrated Inc.

Date: May 18th, 2017

IEEE SCV CAS proudly co-sponsors the IEEE Santa Clara Valley Solid States Circuits Society upcoming technical talk on Part I of two-part seminars on Time-Based Circuits on Thursday May 18, 2017 by Dr. Matt Straayer from Maxim Integrated Inc. The title of the talk will be on:

“Time-Based Circuits – not just the Single Slope!”



Compared to circuits utilizing voltage or current to convey analog signals, time-based circuits offer unique attributes, ranging from simple, area efficient quantization to more complex techniques for time-based processing such as integration, interpolation, and noise shaping. Although time-based circuits are not new, the availability of fast, low-power transistors in advanced process nodes, combined with the challenges of traditional analog design techniques, has renewed interest in time as a signal domain both in academia and in industry. This talk will look at some obvious and more subtle differences between voltage and time-based circuits, and discuss tradeoffs in the context of application requirements. A few advanced state-of-the-art time-based circuits will motivate the audience to consider how time-based circuits can be a useful tool for their own designs.



Matt Straayer studied electrical engineering at University of Michigan and MIT. Currently he is Executive Director, Advanced Research and Development at Maxim, where his group develops architectures and enabling IP for a wide range of products and applications. His experiences include MEMS, RF, frequency generation, data converters, and power, and has found a valuable role for time-based circuits in each of these areas.


Registration Link:

Part II seminar by Prof. Pavan Hanumolu, UIUC, on August 17 is also available on registration page.

Date: May 18, 2017 (Thursday)
, Networking and refreshments
6:30-8:00pm, Technical Talk

Where: Texas Instruments Auditorium (Building E Visitor Center), 2900 Semiconductor Dr, Santa Clara, CA 95051, DirectionsandMap

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