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Events on November, 2018

“The Life of SPICE,” by Dr. Laurence Nagel, Omega Enterprises Consulting

Date: November 15th, 2018


Sponsored by:

IEEE Silicon Valley Solid-State Circuits Society (SSCS)

IEEE Silicon Valley Circuits and Systems Society (CASS)

“The Life of SPICE” by Dr. Laurence W. Nagel Omega Enterprises Consulting

Register here.


The integrated circuit industry thrives on constant change and new technology. It is curious, then, that the SPICE circuit simulation program, in one form or another, has been around the industry for almost fifty years. Engineers entering this business today weren’t even born when I released the first version of SPICE! In this talk, I will chart the journey of SPICE, starting as a teaching program at the University of California, Berkeley, and spreading into industry and launching a cottage industry of software houses writing and supporting “alphabet SPICE.” I also give credit to the early principals in this journey, and share some amusing experiences. No one can say for sure, but I will speculate on how this particular program has evolved and yet stayed pretty much the same. I can think of no other computer program that can make that claim.


Laurence W. Nagel is an independent consultant in the San Francisco Bay Area. He has worked in the integrated circuit industry for almost 50 years. While earning his BS, MS, and PhD degrees at the University of California, he developed the SPICE circuit simulation program which launched a cottage industry of SPICE simulation tools. Mr. Nagel then began a 20 year career at Bell Laboratories which included developing the ADVICE circuit simulation program; participating in the development of the Kull-Nagel bipolar model; designing analog circuits for submicron NMOS processes; working in the AT&T Intellectual Property Division on assertion of patents and negotiation of patent licenses; and serving as project manager in the development of the Celerity circuit simulation program. Mr. Nagel then joined Anadigics, Inc., where he managed simulation of RF integrated circuits; modeling and characterization of GaAs MESFET device processes; and importing silicon CMOS design tools and foundry support. In 1998, Mr. Nagel founded his own company, Omega Enterprises, to consult on analog circuit design, circuit simulation, semiconductor device modeling, and as an expert witness in patent litigation and trade secret misappropriation matters. In 2008, he returned to his native California where he now resides with his wife Jean in Kensington and operates his consulting company Omega Enterprises Consulting.

The seminar is FREE and donation is accepted for refreshments (FREE SSCS/CAS members/$2 IEEE members/$5 non-members)
Eventbrite registration is required for everyone to attend the talk.


Texas Instruments Silicon Valley Auditorium 2900 Semiconductor Dr., Building E, Santa Clara, CA 95051 Directions and Map (to locate Building E).

Time: November 15 (Thursday) evening 6:00PM-8:00PM
Networking and Refreshments: 6:00 PM – 6:30 PM
Technical Talk: 6:30 PM – 8:00 PM

RISC-V Software Ecosystem and Hardware Framework for Faster Silicon Realization

Date: November 14th, 2018


RISC-V is a free and open Instruction Set Architecture enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for future computing design and innovation.

In the true spirit of Chip Chat, which brings hardware, software, system and application designers together, our November event has talk on “Software State of the Union” for RISC-V ecosystem by an excellent speaker Palmer Dabbelt, from SiFive and ” Hardware Frameworks for building custom silicon faster” by Rajesh V, also from SiFive.

Topic : “Software State of the Union” for the RISC-V ecosystem

Speaker : Palmer Dabbelt

Bio : Palmer is currently the RISC-V Software Team Lead at SiFive, where he maintains the RISC-V ports of binutils, GCC, glibc, Linux, and QEMU. Palmer got involved in the RISC-V project when he was a graduate student at UC Berkeley, where he worked on a pair of RISC-V chips and contributed to the RISC-V software ecosystem. He began his career at Tilera, where he spent most of his time working on a port of Sun’s HotSpot Java virtual machine to a pair of Tilera’s ISAs. In addition his MS in Computer Science from UC Berkeley, Palmer holds a BS in Electrical Engineering from the University of Illinois.

Topic : ” Hardware Framework to Enable Faster Idea-to-Silicon Realization”

Speaker : Rajesh V

Bio : Rajesh Varadharajan is currently the Director of Applications engineering at SiFive responsible for configuring and delivering the custom RISCV cores to the customers. Around 14+ years of experience In ASIC and FPGA design, Rajesh started his career in Rambus as ASIC Engineer working on Ethernet, PCIExpress IPs. After a start stint in SanDisk as Application Engineer where he was building INAND validation platforms, he moved back to Rambus Cryptography Division where he was responsible for designing the Consumable crypto firewall chip. Rajesh received his bachelors from University of Madras , India and finished his masters in Vellore Institute of Technology, India

6:30pm – 7:00pm – Registration and Networking
7:00pm – 8:00pm – Tech Talks
8:00pm – 8:30pm – Networking

Registration Link: here

1. Suggested donation is 10/- to cover the expenses.
– Cash
– Venmo to
– Onsite Credit Card payment

2. Confidential Information will not be discussed. Audience is requested
to refrain from asking questions related to confidential information.



– Please register as soon as possible before we run out of space

– Please mark your calendars and do not miss this Chip Chat event


Thanks to Palmer Dabbelt and Rajesh for readily accepting our invitation to give the talk.

Special thanks to IEEE SVC Young Professionals for co-hosting this event.

Chip Chat Committee : Rambabu Pyapali, Hari Sathianathan, Sriram Radhakrishna, Wenbo Yin, Sukriti Kapoor and Nihita Sadhana

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