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2005 Events


“Nanotechnology: A Review of Recent Developments” by Dr. Meyya Meyyappan

Date: February 21st, 2005

“Nanotechnology: A Review of Recent Developments”

by Dr. Meyya Meyyappan, NASA Ames Research Center

 

Presentation available in pdf

Abstract: Nanotechnology refers to the ability of scientists and technologists to manipulate matter at the level of single atoms, and small groups of atoms. Nanotechnology is fast becoming an important and all – encompassing technology, affecting all sectors of global economy . It has enormous potential to deliver significant economic, community, and defense benefits. The technology is expected to spawn a new kind of industrial revolution in the coming decades and holds the promise of scientific breakthroughs in a wide range of fields, has an immense potential for industry and the overall economy, for better health care, and for a sustainable environment.

Nanotechnology is the next great technology wave. It will lead to profound advances in energy, medicine, electronics and other areas: think matter compilers, personalized meds, and inexhaustible power sources.

Dr. Meyya Meyyappan from NSAA AMES will provide a review of recent development in Nanotechnology.

Nanotechnology is an enabling technology with an expected impact on electronics, computing, data storage, materials and manufacturing, energy, transporation, health and medicine, national security and space exploration.

This talk will first outline potential applications in these areas and challenges to be overcome. Specific research results, as examples, in the above areas will also be provided.

 

Bio: Meyya Meyyappan is Director of the Center for Nanotechnology as well as Senior Scientist at NASA Ames Research Center in Moffett Field, CA. He is a founding member of the Interagency Working Group on Nanotechnology(IWGN) established by the Office of Science and Technology Policy(OSTP). The IWGN is responsible for putting together the National Nanotechnology Initiative.

Dr. Meyyappan’s group, consisting of about 60 scientists, has been engaged in various aspects of nanotechnology(see http://www.ipt.arc.nasa.gov). He is a Fellow of the Institute of Electrical and Electronics Engineers(IEEE). He is Fellow of the Electrochemical Society(ECS). He is the IEEE Distinguished Lecturer on Nanotechnology and ASME’s Distinguished Lecturer on Nanotechnology.

For his work and leadership in nanotechnology, he has been awarded NASA’s Outstanding Leadership Medal and Arthur Flemming Award by the Arthur Flemming Foundation and George Washington University. For his contributions to nanotechnology education and training, he has been awarded the 2003-2004 Engineer of the Year award by the San Francisco section of the AIAA. In 2004, he has been awarded President’s Meritorious Award for his contributions to nanotechnology.


“New Approaches For Modeling and Design of High-Frequency Devices” by Dr. Yasser A. Hussein

Date: April 25th, 2005

“New Approaches For Modeling and Design of High-Frequency Devices”

by Dr. Yasser A. Hussein, Stanford University

 

Abstract: Global modeling (electromagnetic-physics-based modeling) of high-frequency devices mandates the integration of circuit, electromagnetics, and device transport physics into a single package. As circuit operation extends into the millimeter and submillimeter-wave regimes, appropriate device models should be employed for the submicron/nano devices embedded in the circuit.

As the operating frequency (or clock speed) increases in circuits, one must treat signals as electromagnetic waves propagating rather than simple voltages and currents. At sufficiently high frequency, such distributed effects even become problematic within individual devices. At even higher frequencies in the terahertz and far-infrared regime, one has to account for radiation and absorption including the interaction with the whole environment. Further, appropriate device models should be employed as the device size approaches the micro/nano scale. This problem requires development of new and efficient multi-physics simulation (CAD) tools that combine electromagnetic theory, semiconductor transport models, and circuit models into a single package.

In this talk, a review of global modeling of semiconductor devices will be presented. Numerical challenges associated with developing such models will also be discussed. Several applications with different electromagnetic and device physics coupling mechanisms will be provided. This includes modeling of high-frequency PIN switches, modeling of high-frequency multifinger FETs, and finally modeling and design of on-chip THz radiation sources. Efficient techniques for S-parameters and radiation efficiency calculations of complex microwave structures will also be presented.

 

Bio: Yasser A. Hussein (M’03) received the Ph.D. degree in Electrical Engineering from Arizona State University, Tempe, AZ, USA in 2003, and the B.S. and M.S. degrees, both in Electrical Engineering, from Cairo University, Cairo, Egypt, in 1995 and 1998. He is currently a Post-Doctoral Research Faculty at Stanford Linear Accelerator Center (SLAC)-Stanford University. He developed and taught a new graduate course (EE 419- high-frequency models of semiconductor devices) in the Electrical Engineering Department at Stanford University. His current research interests include high-frequency computer-aided-design (CAD) of micro/nano devices, electromagnetics, microwaves, computational electromagnetics, semiconductor device simulations, and wave-device interactions.

Dr. Hussein is a Member of IEEE, an elected Member of Commission D of the United States National Committee of The International Union of Radio Science (USNC-URSI), and a nominated member for Sigma Xi. He has around 30 publications including journal papers (IEEE T-MTT), conference digest papers (IEEE MTT-s IMS and IEEE AP-S/URSI), and recently a book chapter on CAD development for microwave and millimeter-wave applications (Kluwer Academic Publishers). He serves as a technical reviewer for several journals.


“Silicon Photonics: Opportunity, Applications & Recent Results” by Dr. Mario Paniccia

Date: May 16th, 2005

“Silicon Photonics: Opportunity, Applications & Recent Results”

by Dr. Mario Paniccia, Intel Corporation

 

Presentation available in pdf

Abstract: Silicon photonics especially that based upon silicon on insulator (SOI) has recently attracted a great deal of attention since it offers an opportunity for low cost opto-electronic solutions for applications ranging from telecommunications down to chip-to-chip interconnects. The presentation will give an overview of research being done at Intel in the area of Silicon Photonics. The presentation will discuss some of the practical issues and challenges with processing silicon photonic devices in a high volume CMOS manufacturing environment and present some of the recent results including the recent breakthroughs in the area of Raman amplification and CW lasing in silicon.

 

Bio: Dr. Mario Paniccia is currently the Director of Photonic Technology Lab at Intel Corporation. Mario currently directs a research group with activities in the area of Silicon Photonics. The team is focused on developing silicon-based photonic building blocks using standard CMOS processing for future use in enterprise and data center communications. Mario has worked in many areas of optical technologies during his career at Intel including optical testing for leading edge microprocessors, optical communications and optical interconnects. Mario earned a B.S. degree in Physics in 1988 from the State University of New York at Binghamton and a Ph.D. degree in Solid State Physics from Purdue University in 1994.


“Wireless Sensor Networks: Trends, Applications, and Development Platforms” by Dr. Hamid Aghajan

Date: June 6th, 2005

“Wireless Sensor Networks: Trends, Applications, and Development Platforms”

by Dr. Hamid Aghajan, Stanford University

 

Abstract: Energy and bandwidth constraints are major concerns in developing applications in wireless sensor networks. Hence, most traditional applications in this field are designed to deal with input data that is of low-bandwidth nature. In this talk we examine the possibilities in using high-bandwidth input data while the network communication is maintained at low-bandwidth levels. In particular, we will provide examples of how on-board computing and collaborative processing techniques can be employed to address problems in network self-organization and tracking applications using distributed image sensors. Several hardware and software platforms developed at the Wireless Sensor Networks Lab at Stanford University that enable efficient algorithm development and testing for these applications will also be introduced.

 

Bio: Hamid Aghajan is a consulting professor in the Department of Electrical Engineering at Stanford University, where he has helped establish and now supervises the Wireless Sensor Networks Laboratory with sponsorship of Professor Andrea Goldsmith. Hamid has ten years of industrial experience in algorithm design for application domains in wireless communications, optical telecommunications, biotechnology, and semiconductor manufacturing industries. He has consulted for several corporations, research labs, startups, and investors on the technical and commercial aspects of various wireless technologies as well as image processing and sensor networks applications. He was a co-founder and vice president of an optical telecom start-up company in 2001, and has also served on the Board of Advisors of high technology companies active in various wireless sensor networks applications.

Hamid is currently supporting research programs of a group of students at Stanford University on various aspects of wireless sensor networks with an emphasis on decentralized and collaborative processing methods for automated network node localization, applications of wireless image sensor networks, and RFID-enabled networks. In addition, he is supervising the development of several hardware and simulation platforms at the lab, including the design of two new wireless motes, which enable effective algorithm and application development in these fields. Hamid has published numerous journal and conference papers and holds 5 US patents. He has a Ph.D. degree in Electrical Engineering from Stanford University.


“A Gentle Introduction to Microprocessor Testing” by Dr. Sreejit Chakravarty

Date: October 17th, 2005

“A Gentle Introduction to Microprocessor Testing”

by Dr. Sreejit Chakravarty

 

Abstract: This talk is aimed at the general audience who are not familiar with Microprocessor testing. The basics of high volume manufacturing (HVM) testing will be introduced. The major cost components of HVM testing and the challenges going forward will be highlighted. Detailed discussion on any given topic will be left to the Q&A session.

 

Bio: Dr. Sreejit Chakravarty completed his BE in electrical and electronics engineering from BITS, Pilani, India (BS), and the MS and PhD in Computer Science from the State University of New York respectively in 1980, 1983 and 1986. After that he spent about 11 years in academia as an Associate Professor of Computer Science at the State University of New York at Buffalo. Since 1997 he has been with Intel Corporation where he is a Principal Engineer in the Advanced Test Technology group. He is the technical lead in various test technology projects targeted at Intel’s microprocessor products, including defect based testing, scan-based at-speed testing etc. Dr. Chakravarty has published widely in various IEEE journals and conferences, has several patents and has co-authored a book on IDDQ Testing. He served as General Chair, Program Chair and Program Vice-Chair of several IEEE conferences/symposias. He continues to serve on the program and organizing committees of several IEEE conferences. He has delivered several keynote addresses at IEEE sponsored conferences. Sreejit is a fellow of IEEE.


“A Digital Clock and Data Recovery Architecture for Multi-Gigabi/s Binary Links” by Dr. Jeff Sontag

Date: November 21st, 2005

“A Digital Clock and Data Recovery Architecture for Multi-Gigabi/s Binary Links”

by Dr. Jeff Sontag, Synposys

 

Abstract: Multi-Gigabit per second (Gbps) serial binary links are fast replacing traditional parallel data links in many applications. Examples include PCI moving towards PCIexpress and ATA moving towards SATA. Additionally, there exist many other applications with multi-Gbps serial links such as XAUI, FibreChannel and RapidIO. Thus the problem of architecting an effective Clock and Data Recovery (CDR) for multi-Gbps rates is becoming increasingly common. At the same time, the trend is for the serial link to become a peripheral function at the edge of a large ASIC, rather than the core function of a mixed signal ASSP. For this reason, effective solutions must be extremely low in power, implementable in the cheapest of digital process technologies, and easily ported across multiple technologies and speed targets.

In this paper we present and discuss a general architecture that meets these criteria. In section II, we present a small signal model and analysis for CDR’s with bang-bang phase detectors. In section III, we describe and analyze the digital CDR. In section IV, we present measured results that corroborate the analysis of section III. Finally in section V, we summarize the results and describe the advantages of digital CDRs over analog implementations.

 

Bio: Jeff L. Sonntag received the B.S.E.E. degree from Carnegie-Mellon University in 1982, and the M.S.E.E. degree from Cornell University in 1983. He joined Bell Labs in 1982, where he spent 18 years developing high performance mixed signal integrated circuits, focusing on applications in disk drive read channels while his employer evolved into AT&T Microelectronics and Lucent Technologies. In recognition of his contributions in 1998, he was named a “Bell Labs Fellow”. In 2002, he joined Accelerant Networks in the development of high speed serial transceivers, serving variously as mixed signal circuit designer, system architect, and Chief Technical Officer. Since the acquisition of Accelerant by Synopsys in 2004, he continues to develop SerDes IP in his role as Senior Member of Technical Staff.


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