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2006 Events


“EDA Challenges for Low Power Design” by Anand Iyer

Date: January 21st, 2006

“EDA Challenges for Low Power Design”

by Anand Iyer, Cadence

 

Presentation available in pdf

Abstract: Low power techniques in design are becoming prominent because of the growth in mobile applications as well as the higher leakage currents in advanced process technology. Once relegated to wireless and medical designs, the power reduction techniques are widely used in designs today. Designers have a wide choice of low power techniques such as power gating and dynamic voltage frequency scaling. This talk addresses the range of power reduction techniques available to the designer and weighs the relative advantages and disadvantages of these options. Finally, it gives recommendation as to how to decide between these techniques.

 

Bio: Anand K. Iyer is a product marketing director for Encounter platform at Cadence Design Systems, Inc. His main focus is low power design tools. He has published several papers and articles and has been quoted in a recent Electronic Engineering Times article on low power designs. He is closely involved in supporting several low power customer designs. He has been with Cadence for the last six years. Previously, he worked at HAL Computer Systems, wholly owned subsidiary of Fujitsu for 6 years as CAD Manager. He received his MBA from the Santa Clara University in 2002, MSEE from the University of California, Santa Barbara in 1994 and M.Tech in Reliability Engineering from IIT, Bombay in 1992.


“It is about the D in DFM. A holistic approach to Design For manufacturability” by Carlo Guardiani

Date: February 27th, 2006

“It is about the D in DFM. A holistic approach to Design For manufacturability”

by Carlo Guardiani, PDF

 

Abstract: Conventional thinking about DFM positions the activities that go under the name of Design For Manufacturability in the realm of layout polygons manipulation, OPC/RET optimization/verification and mask correction methods.

Although all these activities are certainly key to successful chip manufacturing it is clear that they only involve the physical level (and below) of the design flow, i.e. the one closest to the “M” side of DFM.

In this speech we will show that, analogously to power and timing, also functional and speed yield can be addressed at all design levels, and that actually most of the DFM/DFY opportunities exist at higher levels of abstraction and associated design flow tasks such as RTL design, synthesis, design floor-plan optimization and place & route.

 

Bio: Carlo Guardiani is Senior Director of DFM Engineering and head of the Italian Operations for PDF Solutions, having joined PDF in March of 1999 as Director of Statistical Design. Prior to PDF, he held multiple positions at ST Microelectronics in Agrate (Italy) and Grenoble (France) culminating in being the R&D manager of advanced research in power and timing methodologies. Mr. Guardiani has a degree in physics with Laude from the University of Parma in Italy, holds several US and international patents and is the author of over 40 IEEE Conference and Journal papers.


“Basic Concepts of Statistical Timing” by Vassilios Gerousis

Date: March 20th, 2006

“Basic Concepts of Statistical Timing”

by Vassilios Gerousis, Cadence

 

Abstract: Increasing variability in deep sub micron technologies has become a critical issue in nanometer digital design (below 100 nm). A good understanding of the sources and nature of process variation is key to accurately simulating their impact design. We will examine first the sources of variations and how these variations can be modeled for statistical analysis. Statistical timing addresses the analysis of digital design under both process and environmental variations. Discussion on the algorithmic approaches to efficient SSTA will be covered. We will look into how the propagation of a delay distribution through a circuit can be computed properly. We will also discuss requirements on the characterization and extraction of statistical data in the fabrication lines and they should feed statistical analysis tools.

 

Bio: Vassilios is currently working at Cadence as a senior architect in the digital IC division. He spent 6 years working at Infineon technology In Germany working on advanced design methodology to address challenges in 90 NM and 65 NM silicon technologies. He helped to pioneer low power support in support of 90 NM developments, then he focused on yield-aware design methodology to address 65 nm silicon challenges. He spent 18 years working for Motorola Semiconductor, mostly in advanced design methodology. The work he has done at both Infineon and Motorola, helped to drive commercial EDA support to support next generation silicon process. After graduation with doctorate degree in electrical Engineering from Northeastern University he spent three years at TI working in their ASIC bipolar group. Vassilios Gerousis has been active in industry standards and his latest success is SystemVerilog standardization and industry adoption.


“A High-Performance, Low-Cost Ultra Wideband System” by Dr. Rajeev Krishnamoorthy

Date: April 17th, 2006

“A High-Performance, Low-Cost Ultra Wideband System”

by Dr. Rajeev Krishnamoorthy, TZero

 

Abstract: This talk will give an overview of Tzero UWB chipset and system. TZero has built an all-CMOS chipset which reliably delivers 500 Mbps wireless connectivity. The solution provides exceptionally long range, high robustness to interference, and high link reliability and availability in order to support high-bandwidth video, audio, and data networking.

 

Bio: Rajeev Krishnamoorthy has spent many years working on the development of novel, advanced communications systems.

Prior to founding TZero, Rajeev was at Iospan Wireless, where he was responsible for developing the first commercially available multiple-antenna (MIMO) wireless systems. Rajeev spent the early years of his career at Bell Labs (AT&T/Lucent/Agere).

Part of his tenure was at the wireless LAN division in the Netherlands, where he co-invented and developed the high-speed version of the system that resulted in the 802.11b (Wi-Fi) standard. Rajeev received his BS from Caltech and his PhD from Cornell.

 


“A Fast Stochastic Integral Equation Solver to Model Rough Surface Effects” by Zhenhai Zhu

Date: May 15th, 2006

“A Fast Stochastic Integral Equation Solver to Model Rough Surface Effects”

by Zhenhai Zhu, Cadence Berkeley Laboratories

 

Abstract: Rough surfaces are pervasive in integrated circuits and systems at both on-chip and off-chip levels. They are caused mainly by the imperfection in manufacturing processes such as electroplating and etching. And they can lead to serious performance degradation. For example, extensive experiments have shown that surface roughness can cause the conduction loss on the printed circuit boards to increase by a factor of 3 at high frequencies.

The calculation of the equivalent circuit elements of complicated 3D interconnect structures, so called parasitic extraction, has become a mature sub-field in EDA research and industry. The integral equation based methods have been proven to be the most powerful approaches. But so far the surfaces of those 3D structures have always been assumed to be perfectly smooth. The presence of surface roughness changes the nature of the problem and has unfortunately raised the numerical difficulty of the parasitic extraction to such a new level that even the state-of-the-art parasitic extraction algorithms are not able to handle practical structures.

In this talk, I will show

  • Why the rough surface problem is important
  • A quick review of integral equation based parasitic extraction solvers
  • Why these solvers fail to efficiently solve the rough surface problem
  • The key elements in the proposed fast stochastic integral equation solver (FastSies)
  • The potential applications of FastSies in high frequency electromagnetic analysis of 3D structures with rough surfaces

 

Bio: Zhenhai Zhu received his M.S. and Ph.D. degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology in 2002 and 2004, respectively. He was a Josef Raviv Memorial Postdoctoral Fellow at IBM T.J. Watson Research Center from 2004 to 2005. He joined Cadence Berkeley Laboratories as a Research Scientist in July, 2005.

He is a recipient of IEEE/ACM William J. McCalla 2005 ICCAD Best Paper Award for his work on fast stochastic integral equation solver. At MIT he also developed FastImp, a public-domain fast impedance extraction code, and pfft++, a public-domain fast integral equation solver. FastImp is generally considered as the state-of-the-art academic solver for the high-frequency analysis of 3D interconnects. The code pfft++ has been used to solve various partial differential equations in different engineering applications, such as computational aerodynamics, bio-molecular simulation and drug design, and computational electromagnetics.

His research interests focus on the development of efficient numerical methods for modeling and simulation of high frequency electronic systems. Current research projects include variational model order reduction, statistical timing and lithography simulation.

He lives with his wife and son in the city of Alameda. He likes to jog or bike along coast line, work out in gym and play table tennis and badminton. He was a leading player and co-captain of MIT table tennis team.


Half Day Seminar: “Soft Skills – Things They Don’t Teach at Engineering School”

Date: June 10th, 2006

Half Day Seminar: “Soft Skills – Things They Don’t Teach at Engineering School”

by William Kao, Carl Thormeyer, Eric Pan, Lou Scheffer, Cheryl Kennedy

 

Program available in pdf

Abstract: A soft skill refers to the cluster of personality traits, social graces, facility with language, personal habits, friendliness, and optimism that mark each of us to varying degrees. Soft skills complement hard skills which are the technical requirements of a job. Ideally someone is strong in both technical and personal skills. In this seminar, you will have a chance to listen to five outstanding technical and business professionals presenting various topics and aspects relating to soft skills, with the objective of applying directly some of these techniques to advance your individual career.


“Verification of CML circuits used in PLL contexts with Verilog-AMS” by Jonathan David

Date: October 23rd, 2006

“Verification of CML circuits used in PLL contexts with Verilog-AMS”

by Jonathan David, Scintera Networks

 

Abstract: Differential or Current-Mode Logic (CML) circuits are used in very high-speed applications where standard CMOS gates will not switch fast enough. Due to the size of this market, standard logic design and simulation tools have not been adapted to address this design niche, forcing designers to develop their own tools, or use custom (ie Analog) design tools and simulators. Using Analog simulator for this design space is very time-consuming, limiting the design size that can be worked on in a given timeframe, and usually preventing sufficient verification to be be completed prior to tapeout. Mixed signal simulators using Verilog-AMS netlists are able to address this design space, but examples are not widely available.

In this tutorial presentation Applications of CML logic are introduced, focusing on the Clock Divider for PLL’s operating above 1-2GHz common in communication circuits. An overview of CML circuits and their operation is provided. Starting with a Verilog-A model of a basic gate, the development of a mixed signal model, and the required connect elements and rules are explained, and applied to the simulation of the clock divider. The presentation will close with the application of this circuit to the PLL and the resulting simulation performance improvements.

 

Bio: Jonathan David leads the Mixed Signal Design Verification team at Scintera Networks, http://www.scintera.com. Prior to joining Scintera, he worked with Cadence Design Systems, assisting customers with the adoption and use of Analog and Mixed Signal simulation tools, and with development of Analog Behavioral Models in the Verilog-A and Verilog-AMS languages.

An active IEEE volunteer, and early adopter, he created the first website for the Santa Clara Valley Section, was instrumental in the founding of both the Solid-State Circuits and Circuits and Systems chapters in the Section, and recently as the chair of the SCV-PACE group, created the first IEEE officer blog in the section at http://ieee-jbdavid.blogspot.com.


“Challenges and Technology behind 10GBASE-LRM and Multi-Gigabit Communications” by Abhijit Phanse

Date: November 20th, 2006

“Challenges and Technology behind 10GBASE-LRM and Multi-Gigabit Communications”

by Abhijit Phanse, Scintera Networks, Inc.

 

Abstract: With the continued popularity of high-bandwidth applications such as Skype and YouTube, the need for higher capacity public and private networks has become critical. At the same time, the new applications attract new users to the Internet, and further increase the bandwidth requirements. While new network installations can be planned for a certain amount of growth capacity, expanding the capacity of existing network infrastructure can be prohibitively expensive if additional cabling must be installed.

The bulk of the existing Enterprise backbone networks consist of relatively inexpensive multimode fiber, often installed when the maximum data transmission rate was 100Mb/s. Over time, these networks were upgraded to 1Gb/s, and are now reaching their maximum capacity, obviating a move to 10Gb/s links. At typical transmission distances of 100-220m, modal dispersion prevents the use of data rates beyond 3Gb/s. An early but expensive approach to operating at the 10Gb/s data rate uses Wavelength Division Multiplexing (WDM) requiring 4 lasers, and 4 receivers per channel (LX4). Recently, the IEEE has approved a new 10Gb/s Ethernet specification, 802.3aq (10GBASE-LRM), which is a more cost effective approach in using signal processing techniques to overcome the fiber impairments and allowing 1 wavelength to carry data at 10Gb/s, at up to 220m.

The presentation will cover the Enterprise backbone market, the technical challenges, and the technology approaches being used to make this protocol practical.

 

Bio: Abhijit Phanse was Scintera’s founding CEO and grew the Company to develop its Advanced Signal Processing Platform (ASPP?) technology and become a leader in multi Gigabit signal processors. Since February 2006, Abhijit has assumed the role of president and chief operating officer.

Abhijit has over 12 years of broad range semiconductor experience in the development and successful commercialization of solutions for high speed Communication and Networking applications. Prior to co-founding Scintera in August 2001, Abhijit led the development of three generations of successful Ethernet technologies and products at National Semiconductor – 100M Ethernet, 1000 Base-T Gigabit Ethernet, and 10 Gigabit Ethernet. He has played a defining role in the development of the IEEE Gigabit Ethernet and 10 Gigabit Ethernet Standards. He was instrumental in starting the efforts within the IEEE to incorporate intelligent electronic signal processing solutions at 10G for enabling cost effective upgrades to enterprise networks. Abhijit has over twelve international publications and holds over thirty patents. He holds an MS in Electrical Engineering from the University of Central Florida and a Bachelor of Technology in Electrical Engineering from the Indian Institute of Technology, Bombay, and is a Member of the IEEE.


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