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Date: January 31st, 2019
Lecture by Dr. Ratnesh Kumar “Vehicle Re-identification for Smart Cities: A New Baseline Using Triplet Embedding”



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2007 Events

“A Technology Enabler for High Efficiency Amplifier Applications” by Jerry Lee

Date: February 26th, 2007

“A Technology Enabler for High Efficiency Amplifier Applications”

by Jerry Lee, MwT


Abstract: Performance of an amplitude modulator architecture that enables the potential efficiency/cost advantages will be presented. In this presentation, one of the most crucial components, the amplitude modulator, of the envelope elimination and restoration transmitter will be presented and discussed. Over the past decades, many new modulation schemes have been developed to offer higher data rates and better spectral efficiency for the same bandwidth. These modulations format present difficulties for power amplifier because of the statistics of the RF envelope. Conventional class A amplifiers are inefficient for modulations with high crest factors. Some class AB amplifiers including feed forward and pre-distortion methods do improve non-linearity but contribute to efficiency degradation and higher cost. Most recent applications include Doherty amplifiers that improve efficiency by 10% factor. For Doherty amplifier ( an envelope elimination and restoration transmitter) , the overhead circuitry and complexity is similar to feed forward and/or pre-distortion. However, the die size is effectively 6 dB (power rating) smaller than its counterpart, hence the implementation cost is lower. Performance of an amplitude modulator architecture that enables the potential efficiency/cost advantages will be presented. This amplitude modulator delivers 100 watts into 3 ohms in less than 10 nanoseconds. The voltage gain is 10 and provides voltage control from its input to any voltage from 0 to 28 volts. The bandwidth of this amplitude modulator is greater than 50 MHz and its distortion level are better than -50 dBc.


Bio: Mr. Jerry Lee received his BS and MS from UC Berkeley and Stanford respectively. He has been working in the Microwave industry for over 25 years. In the last 7 years, he was at Tropian, Inc working on polar modulation techniques developing and designing applications for high power 2G and 3G base stations. He later joined Spectrian/Remec and continued to develop new pre-distortion applications for 3G and 4G base stations utilizing envelope elimination and restoration techniques. He is presently at MwT as their CTO.

“Modular Testing of Core-Based System-on-Chip Integrated Circuits” by Krishnendu Chakrabarty

Date: March 19th, 2007

“Modular Testing of Core-Based System-on-Chip Integrated Circuits”

by Krishnendu Chakrabarty, Duke University


Abstract: Variation Robustness for Analog/Mixed-Signal, Custom Digital and Memory Design Patrick G. Drennan, Ph.D. Chief Technology Officer Solido Design Automation As process technologies and supply voltages shrink, designers are faced with a pressing need to address systematic and random sources of variation in a more deliberate and thorough way. Accounting for variation within the flow of design has not progressed commensurate with the process technologies. We still rely on best-, worst- case corners, mismatch plots and maybe a Monte Carlo verification if there is enough time. It is time for a new approach. This talk will begin with a brief review of the physical phenomena and industry standard device models for variation sources, including random local and global variations and systematic proximity effects. New techniques to accelerate, increase accuracy and derive more information from statistical variation analysis will be presented.


Bio: Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively, all in Computer Science and Engineering. He is now Professor of Electrical and Computer Engineering at Duke University. Dr. Chakrabarty is a recipient of the National Science Foundation Early Faculty (CAREER) award and the Office of Naval Research Young Investigator award. His current research projects include: testing and design-for-testability of system-on-chip integrated circuits; microfluidic biochips; microfluidics-based chip cooling; wireless sensor networks. Prof. Chakrabarty has authored four books Microelectrofluidic Systems: Modeling and Simulation (CRC Press, 2002), Test Resource Partitioning for System-on-a-Chip (Kluwer, 2002), Scalable Infrastructure for Distributed Sensor Networks (Springer, 2005), and Digital Microfluidics Biochips: Synthesis, Testing, and Reconfigutaion Techniques (CRC Press, 2006) and edited the book volumes SOC (System-on-a-Chip) Testing for Plug and Play Test Automation (Kluwer, 2002) and Design Automation Methods and Tools for Microfluidics-Based Biochips (Springer, 2006). He is also an author of the forthcoming book Adaptive Cooling of Integrated Circuits using Digital Microfluidics (Artech House, April 2007). He has contributed over a dozen invited chapters to book volumes, and published over 240 papers in archival journals and refereed conference proceedings. He holds a US patent in built-in self-test and is a co-inventor of a pending US patent on sensor networks. He is a recipient of best paper awards at the 2007 IEEE International Conference on VLSI Design, the 2005 IEEE International Conference on Computer Design, and the 2001 IEEE Design, Automation and Test in Europe (DATE) Conference. He is also a recipient of the Humboldt Research Fellowship, awarded by the Alexander von Humboldt Foundation, Germany.

Prof. Chakrabarty is a Distinguished Visitor of the IEEE Computer Society for 2006-2007 and a Distinguished Lecturer of the IEEE Circuits and Systems Society for 2006-2007. He is an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on VLSI Systems, IEEE Transactions on Circuits and System I, ACM Journal on Emerging Technologies in Computing Systems, an Editor of IEEE Design & Test of Computers, and an Editor of Journal of Electronic Testing: Theory and Applications (JETTA). He is a member of the editorial board for Microelectronics Journal, Sensor Letters, and Journal of Embedded Computing, and he serves as a subject area editor for the International Journal of Distributed Sensor Networks. In the recent past, he has also served as an Associateg Editor of IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processingg. He is a senior member of IEEE, a senior member of ACM, and a member of Sigma Xi. He serves as Vice Chair of Technical Activities in IEEE’s Test Technology Technical Council, and is a member of the program committees of several IEEE ACM conferences and workshops. He served as the chair of the emerging technologies subcommittee for the IEEE Int. Conf. CAD (2005-2006), and chairs the subcommittee for new, emerging, and specialized technologies for the 2006-2007 IEEE ACM Design Automation Conference. He served as Tutorials Chair for the 2005 IEEE International Conference on VLSI Design and Program Chair for the 2005 IEEE Asian Test Symposium. He is the designated Program Chair for the CAD, Design, and Test Conference for the 2007 IEEE Symposium on Design, Integration, Test, and Packaging of MEMS MOEMS (DTIP’07). He delivered keynote talks at the International Conference & Exhibition on Micro Electro, Opto, Mechanical Systems and Components (Munich, Germany, October 2005), the International Conference on Design and Test of Integrated Systems (Tunis, Tunisia, September 2006), as well as invited talks on biochips CAD at several other conferences.

“Characterization and Electromagnetic Synthesis and Verification of Inductive Structures for RF Design in Sub-100nm Nodes” by Dr. Jinsong Zhao

Date: April 16th, 2007

“Characterization and Electromagnetic Synthesis and Verification of Inductive Structures for RF Design in Sub-100nm Nodes”

by Dr. Jinsong Zhao, Lorentz Solution, Inc.


Abstract: For RF designs in sub-100nm nodes, lately the efforts to design and verify advanced inductive structures have intensified to achieve three goals: design productivity, accurate prediction of device physics, and optimal performance. In a production design environment, devices must be high-performance and conform to stringent manufacturing requirements. While electromagnetic analysis is the natural physics-based device modeling method, the enormously complicated design data and difficult use of genereal-purpose EM solver leave most of today’s inductive structures unoptimized and poorly modeled. This presentation covers the basic device characterization methods, physics behind the innovative designs, and the electromagnetic synthesis and verification of those devices in a tightly integrated design environment. We also cover the challenges of making the electromagnetic capabilities accessible to designers and architectural and physics thinkings to make such capabilities available.


Bio: Dr. Jinsong Zhao, founder and president of Lorentz Solution, Inc, leads the company’s efforts in developing and delivering the industry’s first IC-focused electromagnetic design and verification solution. Several world’s top semiconductor companies adopted Lorentz products to design the most challenging RFIC products. Dr Zhao has authored two pending patents for Lorentz. Prior to founding Lorentz, Dr. Zhao was a Sr Member of Consulting Staff at Cadence Design Systems SpectreRF team, leading the R&D effort in mixed-signal parasitic extraction, substrate coupling analysis, and RF behavioral system modeling. Prior to that, Dr Zhao spent one year at Bell Labs and was co-author of three US patents in RF modeling and IC module design. Dr. Zhao received his BS/MS in Electrical Engineering from Tsinghua University at Beijing , and earned his PhD in Computer Engineering from UC Santa Cruz. Dr Zhao also holds an MBA from UC Berkeley.

Saturday Half Day Tutorial “Broadband and Radio Frequency Circuit Analysis and Design In CMOS Technology Part-II”

Date: September 15th, 2007

“Broadband and Radio Frequency Circuit Analysis and Design In CMOS Technology Part-II”

by Dr. John Choma, USC


Program available in pdf

Abstract: This tutorial, a continuation of the Sept 2006 event, will familiarize engineering professionals with both classic and innovative new broadbanding techniques for CMOS technology amplifiers appropriate for state of the art communication system applications, with a focus on Distributed Amplifiers. A unified circuit broadbanding strategy is propounded, as is a practical methodology for the monolithic realization of narrowband radio frequency (RF) amplifiers. Because broadband and RF design necessarily entails the incorporation of suitable matching filters in signal flow paths, a reasonably extensive discussion of lossless filter architectures is incorporated in the tutorial. All theoretic and conceptual disclosures are verified through the results of realistic SPICE simulations.


Bio: John Choma earned his B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Pittsburgh in 1963, 1965, and 1969, respectively. He is a Fellow at Scintera Networks in San Jose, California, and is Professor of Electrical Engineering at the University of Southern California, where he teaches undergraduate and graduate courses in electrical circuit theory, filters, and analog integrated electronics. Prof. Choma also holds a joint USC appointment as Professor of System Architecture Engineering. Prof. Choma has consulted extensively in the areas of broadband analog and high-speed digital integrated circuit analysis, design, and modeling.

Prior to joining the USC faculty in 1980, Prof. Choma was a senior staff design engineer in the TRW Microelectronics Center in Redondo Beach, California. His earlier positions include technical staff at Hewlett-Packard Company in Santa Clara, California, Senior Lecturer in the Graduate Division of the Department of Electrical Engineering of the California Institute of Technology, lectureships at the University of Santa Clara and the University of California at Los Angeles, and a faculty appointment at the University of Pennsylvania.

Prof. Choma, the author or co-author of some 150 journal and conference papers and the presenter of more than sixty invited short courses, seminars, and tutorials, is the 1994 recipient of the Prize Paper Award from the IEEE Microwave Theory and Techniques Society. He is the author of a Wiley Interscience text on electrical network theory and a forthcoming World Scientific Press text on feedback circuit design for communication system applications. Prof. Choma has contributed several chapters to five edited electronic circuit texts, and he is an area editor of the IEEE/CRC Press Handbook of Circuits and Filters.

Prof. Choma has served the IEEE Circuits and Systems Society as a member of its Board of Governors, its Vice President for Administration, and its President. He has been an Associate Editor and Editor-In-CChief of the IEEE Transactions on Circuits and Systems, Part II. He is an Associate Editor of the Journal of Analog Integrated Circuits and Signal Processing and a former Regional Editor of the Journal of Circuits, Systems, and Computers.

A Fellow of the IEEE, Prof. Choma has been awarded the IEEE Millennium medal, and he has received three awards from the IEEE Circuits and Systems Society; namely, the Golden Jubilee Award, the 1999 Education Award, and the 2000 Meritorious Service Award. He is also the recipient of several local and national teaching awards. Prof. Choma has served as a “Distinguished Lecturer” in the IEEE Circuits and Systems Society.

“Transceiver Designs for Multicarrier Transmission” by Prof. Yuan-Pei Lin

Date: September 17th, 2007

“Transceiver Designs for Multicarrier Transmission”

by Prof. Yuan-Pei Lin, National Chiao-Tung University, Taiwan


Distinguished Lecture joint meeting with SCV-ComSoc and SCV-SPS

Abstract: The multicarrier transceiver has found applications in a wide range of wired or wireless transmission channels. It is typically called DMT (discrete multitone) for wired DSL (digital subscriber loops) applications such as ADSL (asymmetric DSL) and VDSL (very high-speed DSL), and called OFDM (orthogonal frequency division multiplexing) for wireless LAN (local area network) and broadcasting applications such as digital audio broadcasting and digital video broadcasting. For wireless transmission, the channel profile is usually not available to the transmitter. The transmitter is typically channel independent and there is no bit/power allocation. Moreover having a channel independent transmitter is of vital importance for broadcasting applications, where there are many receivers with different transmission paths. In wired DSL applications, the channel does not vary rapidly. This allows the receiver to send channel profile back to the transmitter through a reverse channel. In this lecture, we consider optimal transceiver design for two cases: (i) channel profile available at the transmitter; (ii) channel profile not available at the transmitter. In the first case, the transmitter is channel independent and the channel dependent part of the transceiver should be only at the receiver. The optimal transceiver that minimizes bit error rate rate subject to the same transmission power will be designed. For the second case, bit and power allocation can be used to exploit the disparity among the subchannel noise variances. The optimal transceiver that minimizes transmission power subject to the same transmission bit rate and the same bit error rate will be derived. Substantial gain can be achieved using the optimal transceiver, especially for moderate number of subcarriers. The popularity of system-on-chip (SOC) integrated circuits has led to an unprecedented increase in test costs. This increase can be attributed to the difficulty of test access to embedded cores, as well as long test development and test application times. This talk will present test resource partitioning techniques that facilitate low-cost SOC test. Topics to be covered include the recent IEEE 1500 standard for testing core-based SOCs and techniques for modular testing of digital SOCs. Test planning methods that involve the use of wrappers and test access mechanisms will be discussed. Test scheduling techniques for the concurrent testing of embedded cores at the SOC level will also be presented. Together, these techniques offer SOC integrators with the necessary means to manage test complexity and reduce test costs.


Bio: Prof. Yuan-Pei Lin (S’93-M’97). IEEE CAS Distinguished Lecturer, 2006-2007. She received the B.S. degree in control engineering from the National Chiao-Tung University, Taiwan, in 1992, and the M.S. degree and the Ph.D. degree, both in electrical engineering from California Institute of Technology, in 1993 and 1997, respectively. She joined the Department of Electrical and Control Engineering of National Chiao-Tung University, Taiwan, in 1997. Her research interests include digital signal processing, multirate filter banks, and signal processing for digital communication, particularly the area of multicarrier transmission. She is a senior member of IEEE. She was a recipient of 2004 Ta-You Wu Memorial Award for outstanding research. She is currently an associate editor for IEEE Transaction on Signal Processing, EURASIP Journal on Applied Signal Processing, and Multidimensional Systems and Signal Processing of Academic Press.

“Full-Chip Electro-Thermal Simulation using Loosely Coupled Electrical and Thermal Simulators” by Ranjit Chandra

Date: October 15th, 2007

“Full-Chip Electro-Thermal Simulation using Loosely Coupled Electrical and Thermal Simulators”

by Ranjit Chandra, Gradient Design Automation


Abstract: Current IC design trends calls for integration of power transistors within high-performance mixed-signal designs. Because of the increased power densities caused by such trends, temperature variations within the chip need to be taken into account to achieve cost-effective and reliable chip designs. This session will discuss the following: (1) Potential temperature hazards in IC designs and the need for electrothermal analysis; (2) The challenges of full-chip 3D temperature analysis of IC designs; (3) A temperature- aware methodology that uses detailed temperature information for design improvements of mixed-signal chip designs; (4) An effective temperature- aware design flow at AMIS using Cadence Spectre electrical circuit simulation and thermal analysis tools from Gradient Design Automation. AMIS and Gradient collaborated on a thermal analysis project that allows detailed 3D full-chip temperature distribution within the chip to be calculated and visualized early in the design cycle before taping out. Such temperature checking capability is useful for predicting potential temperature hazards under steady state and transient temperature conditions. Traditional methods of temperature estimates based on power and package parameters do not provide sufficient details while commercial mathematical software tools lack the accuracy needed in contemporary chip-level designs. Using layout and netlist data available in the Cadence design environment, an automated flow has been developed that annotates instance-specific temperatures to Spectre simulation to obtain true temperature- aware power from it. The resulting temperature information is used for floorplanning to reduce design guardbands and potential circuit malfunctions.


Bio: Ranjit founded Gradient Design Automation in 2003. Previously, he was VP of technology at Magma Design Automation, where he focused on signal integrity, power and EM. He was a co-founder and VP of engineering of Moscape Inc., which was acquired by Magma in 2000. Rajit held key positions at Cadence Design where he developed tools for timing-driven designs and authored the industry standard format for timing data exchange (SDF). He worked as a performance verification team lead at Intel Corp. Rajit received his B.Tech and M.Tech in Radio Physics & Electronics from Calcutta University, India, and his PhD (EE) from London South Bank University, UK. He is a Senior Member of the IEEE, and was instrumental in re-forming the IEEE Santa Clara Valley Circuits and Systems chapter, serving as its first chair.

“China IC Design Industry Status Today” by Bob Pau

Date: November 19th, 2007

“China IC Design Industry Status Today”

by Bob Pau, Cadence


Abstract: The world is flattened due to out-sourcing and off-shoring. China has already become the largest importer for electronic components now. Of the $247 Billion high tech imports in China in 2006, $130 Billion were electronic components and equipments. (China statistics in 2007, reported by MOST) China is also entering second year of 11th-5-year plan. New government policy and aids just come out to support electronics eco-system and several industrialization efforts on some application markets. Electronic design business is heating up in China as domestic companies emerge to take advantage of newly chinese made standards. Some domestic companies also went public in NASDAQ, such as ViMicro, Action and Spreadtrum. Chinese domestic IC design houses will continue to strengthen their design capabilities in order to reduce reliance on imported components. Buying from domestic IC houses will help domestic OEMs to reinforce their competitive positions. In this talk, we will answer many questions raised by you and tackles issues including:

  • What is current status of IC industry in China?
  • What is current china government policy?
  • What is the strategy for 11-th 5 years plan?
  • Who are top players now in China?
  • What are they doing to take advantage of strong demand?
  • Who will be the Chinese equivalent Samsung or Broadcom in the future?
  • What is hot products in China for IC design?
  • What is trend in China on electronic design?
  • What is challenges that China design house facing?
  • How can IC design industry improve its design capabilities?
  • Where to set up your own R&D center?
  • What you can do in Silicon Valley to catch those opportunities?
  • What role will you play?

No slides will be posted for this talk. You have to attend to learn the news.


Bio: Bob Pau is a Methodology Architect working in Cadence for six plus years now, focused on RF/AMS SOC design. He worked in China for a year in 2005 to support China IC design houses, then traveled back to China every quarter since 2006. Before he joined Cadence, he spent 14 years in the semiconductor industry in various design, product definition, consulting, application, sales, and marketing roles at leading companies such as Motorola, Harris, Zilog, Infineon, NEC and National. He holds a First Class Engineering degree in RF Communications from University of Bradford, UK. He is a senior member of IEEE, a reviewer for Trans. MTT and a founding member for CAS Santa Clara Chapter.

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