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Date: September 21st, 2018
IEEE Circuits and Systems Society-Silicon Valley (CAS-SV) Artificial Intelligent For Industry Forum



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2012 Events

“All-Digital Transmitter” by Kostas Galanopoulos

Date: January 16th, 2012

“All-Digital Transmitter”

by Kostas Galanopoulos, National Technical University of Athens


Presentation available in pdf

Abstract: Wireless transceivers are some of the few remaining analog-intensive super-blocks in modern Systems-On-Chips. Designing their RF/analog blocks, in contrast to digital blocks, requires significant effort and time due to limited automation and porting capability in the design process. In addition, RF sub-blocks may require advanced fabrication technologies which are much more expensive than standard CMOS ones. Over the past decades, major effort has been dedicated in replacing many analog blocks by digital ones, e.g. frequency synthesizers and base-band signal processors.

The proposed architecture of a purely digital transmitter can be implemented in digital FPGA or ASICs. It is very versatile and can be easily modified to accommodate most of the commonly used modulation schemes (PM, AM, QAM, BPSK, FSK, QPSK etc.) as well as to operate in any desirable frequency band supported by the FPGA or ASIC technology used. It provides an alternative to popular analog-RF architectures offering extremely fast concept-to-market time, low cost, minimal chip-area and power requirements while achieving performance, adequate for many wireless applications.

A live demo of the “All – Digital Transmitter”, with all of its components (Frequency Synthesizer, Modulator, ADC for analog Audio acquisition) implemented within a mini FPGA board (XuLA-50 / Xilinx Spartan 3A), will be presented.

This work has been supervised by Prof. Paul Sotiriadis of the National Technical University of Athens, Greece, (formerly with the Johns Hopkins University) and extends the concepts of all-digital frequency synthesis presented by Drs. Sotiriadis, Staszewski and Xiu, in the S.C. IEEE chapter on August 14-15, 2010.


Bio: Kostas Galanopoulos (S’11) is currently a Ph.D candidate in electrical and computer engineering at the National Technical University of Athens, Greece. He received the Diploma in Computer Engineering and Informatics from the University of Patras, Greece in 2009. He has co-authored seven technical papers in IEEE journals and conferences.

His research interests include the design and optimization of mixed-signal circuit, digital and microprocessor data-path circuits, low power optimization and all-digital frequency synthesis techniques. He regularly serves as a reviewer for IEEE transactions and conferences.

“Next Generation 100 Gigabit Ethernet, Low Power CMOS SerDes, and Signal Integrity Challenges” by Hamid Rategh

Date: February 15th, 2012

“Next Generation 100 Gigabit Ethernet, Low Power CMOS SerDes, and Signal Integrity Challenges”

by Hamid Rategh, Inphi


Abstract: The continued rapid growth in multimedia and mobile traffic over the Internet is driving service providers and datacenter operators to adopt next generation 100 Gigabit Ethernet (100GbE) technology based upon IEEE 802.3ba 100GbE-LR4/ER4 standards. To meet this bandwidth demand, the industry must innovate to achieve high speed, low power, small form factor, and low cost that has been the hallmark of Ethernet technologies. We will discuss a new 100GbE architecture based upon low power CMOS SerDes technology and some of the challenges from signal integrity point of view to meet the higher bandwidth, lower power, higher port density, and lower cost requirements of such systems.


Bio: Hamid Rategh is currently Sr. director of Engineering at Inphi, where he leads the signal integrity efforts for the company’s 100G products. With more than 13 years of industry experience, Dr. Rategh has been responsible for development of wide range of products from RFICs to adaptive equalizers for optical communication and also Mixed-Signal Memory interface products.

Prior to joining Inphi Dr. Rategh was Sr. Director of Engineering at Scientera Networks where he was responsible for the development of adaptive Electronic Dispersion Compensation chips for 10GBASE-LRM using their proprietary analog signal processing technology. Dr. Rategh was also cofounder and VP of Engineering of Tavanza which was later acquired by Celeritek in 2002 and subsequently by Anadigics in 2003.

Dr. Rategh holds a Ph.D. degree in Electrical Engineering from Stanford University.

“New Architecture for Next Generation User-Centric Mobile Device” by Prof. Willie W. Lu

Date: March 12th, 2012

“New Architecture for Next Generation User-Centric Mobile Device”

by Prof. Willie W. Lu, Chief Inventor of OWA Technology and Chairman of Technaut Intellectual Venture


Abstract: The wireless transmission theory tells us that no single wireless transmission technology can provide both broadband high-speed radio transmission and seamless fast mobility capability in a mobile fast-fading propagation model environment unless we reduce the mobile network capacity tremendously. Open Wireless Architecture (OWA) was proposed to balance the above requirements in commercial mobile communications with converged multiple air interfaces in a cost-effective and spectrum-efficient way.

Our research discovers that when the wireless transmission bandwidth is enough, the information processing consumes much more resources and energies than the transmission processing in the mobile device. If we can reduce the processing burdens in the mobile device including baseband signal processing, application processing and networking processing, the overall power consumption can be tremendously minimized and the terminal system can be simplified.

The OWA technology platform has secured enough transmission bandwidth by converging multiple wireless standards in one common platform so that the mobile device can be optimized for best-of-effort high-speed transmission.

By employing a computer server with an IP address as the Virtual Mobile Server, we can configure this server as the mobile cloud serve to handle the processing tasks for the mobile device which becomes the mobile cloud client accordingly.

The OWA mobile cloud architecture tremendously reduces the processing tasks in the mobile device by pushing much processing tasks remotely and synchronously to the virtual mobile server through IP connection based on OWA network access control. The OWA mobile device is open to various carriers selected and optimized by mobile user.

The OWA architecture also facilitates the next generation SIM system supporting multiple air interfaces and open OS virtual machine interface supporting multiple operating systems for the future mobile device.

This seminar relates to the next generation iPhone and Android smartphone evolutions, both in device systems and in wireless transmissions.


Bio: Dr. Willie Lu was former consulting professor of Stanford University, member of FCC TAC, visiting professor of Chinese University of Hong Kong, chief architect of Infineon Technologies and is now adjunct professor of Zhejiang University of China with expertise in advanced wireless and mobile communications. He is worldwide well-known for his invented Open Wireless Architecture (OWA)® core technology which is being widely used in mobile handheld devices and portable devices by many Fortune 500 companies both in the Silicon Valley and global. He founded many world-class technology events including World Wireless Congress®, Mobile World Congress®, Global Mobile Congress®, Open Mobile Summit® and 4G Summit with over 100,000 global wireless professionals involved in his events. Dr. Lu started Intellectual Property Law in 2004 and has been practicing actively in US Patent Laws and Trademark Laws, and specialized in reviving the finally-rejected cases and evaluating the patent cases for both leading industries and start-ups. Prof. Lu is now also Chairman of Technaut Intellectual Venture and Principal Partner of Delson IPR Group with business both in US, EU and China.

Prof. Lu has near 20 years’ experiences in mobile wireless technology, about 8 year’s in IPR laws and 15 years in international policies, government relations and regulatory affairs. He is senior advisor for many government authorities across the global and technical advisor for several IPR courts in US and EU.

“A 16-Gb/s Near-Ground Transceiver with Receive Replica Transconductance Termination Calibration” by Kambiz Kaviani

Date: April 23rd, 2012

“A 16-Gb/s Near-Ground Transceiver with Receive Replica Transconductance Termination Calibration”

by Kambiz Kaviani, Rambus Inc.


Abstract: In this talk a bi-direction differential low-common mode source-series-terminated transceiver operating up to 16-Gb/s data rate is presented. The transceiver is equipped with a number of novel architecture and circuit ingredients to enable reliable data communication over a band-limited channel while maintaining low power efficiency. Specifically, a compact voltage-mode driver and equalizer in the transmitter, and a calibrated fast-response decision feedback equalizer in the receiver are deployed to compensate channel inter-symbol interference. Also, the receiver employs a replica transconductance termination calibration to terminate the communication channel accurately in presence of the receiver input loading. The receiver further incorporates common mode to differential gain cancellation and in-situ equalization calibration for reliable data reception at 16Gb/s over a 3” FR4 PCB memory link with 15dB loss at Nyquist frequency.


Bio: Kambiz Kaviani received the B.S. degree from Sharif University of Technology, Tehran, Iran, in 1994, and the M.S. and Ph.D. degrees from Stanford University, Stanford, CA, both in electrical engineering, in 1999 and 2003, respectively. He is currently a Principal Engineer at Rambus Inc., Sunnyvale, CA, developing high-performance data interface technologies for SERDES, XDRTM, DDR, LPDDR and GDDR platforms. During the summer of 1998, he was with RadioLAN Corporation, Sunnyvale, CA, where he was involved in wireless local area network (WLAN) developments. At Stanford, he was focusing on high-speed and high-precision VLSI data converters and macro-electro-mechanical systems (MEMS). His main interests include high-performance CMOS mixed-signal and RF integrated circuits and systems. Dr. Kaviani was a co-recipient of the 2002 outstanding paper award of the IEEE Ultrasonic, Ferroelectrics, and Frequency Control Society and 2008 CICC best paper award. He has authored or coauthored more than twenty technical papers and patent applications and was a member of the Iranian team in the 21st international Physics Olympiad, Groningen, The Netherlands.

“Modern Antenna Design for Wireless Communications: Challenges and Perspectives” by Steve H. Wong

Date: May 30th, 2012

“Modern Antenna Design for Wireless Communications: Challenges and Perspectives”

by Steve H. Wong, Acting Assistant Professor, Stanford University


Abstract: It is now at a fascinating time in the history of the wireless communications. Numerous wireless communications systems have been successfully developed in recent years. Wireless devices such as cell phones, tablets, laptops, Bluetooth earphones, game pad controllers, GPS receivers and security sensors are very common in our daily life. They require different kinds of antennas with different characteristics for enhancing their performance in connectivity, stability and data rate. Modern antenna designs are required to be small in size and wide in bandwidth, which are contradicting requirements, as governed by the well-known Chu’s limit. This seminar provides participants with comprehensive coverage of a wide variety of small antenna designs related to mobile communications, satellite communications, and millimeter wave applications. The development of small antennas for modern wireless communications with different generic antenna technologies will be given. Major milestones, design challenges and perspectives will be discussed.


Bio: Hang WONG received the B.Eng., M.Phil., and Ph.D. degrees in electronic engineering from City University of Hong Kong in 1999, 2002 and 2006, respectively. He joined the State Key Laboratory (SKL) of Millimeter Waves, in Hong Kong SAR, China, in 2008 as senior engineer; and he is currently served as Acting Assistant Professor in the Department of Electrical Engineering, Stanford University. His research interests include design of broadband antennas, small antennas, GPS antennas, millimeter wave antennas, and Terahertz devices and applications. He is the co-author of some antenna research book chapters. Dr. Wong was awarded the Outstanding Research Thesis Award from City University of Hong Kong in 2002. He received the Microwave Prize at the Asia Pacific Microwave Conference 2006 held in Yokohama, Japan; and received the Best Paper Award at the International Symposium on Antennas and Propagation 2008 in Taipei. He received 2011 State Technology Invention Award presented by the Ministry of Science and Technology of the P.R. China. He was Publication and Publicity Chair of 2008 International Symposium on Antennas and Propagation (ISAP), and Publication Chair of 2011 IEEE International Workshop on Antenna Technology (IWAT). He is currently the chair of the IEEE Hong Kong Section of the Antennas and Propagation (AP) / Microwave Theory and Techniques (MTT) Chapter.

“Recent Advances on Error Correction Coding with non-binary LDPC Codes” by Prof. David Declercq

Date: June 28th, 2012

“Recent Advances on Error Correction Coding with non-binary LDPC Codes”

by Prof. David Declercq, ENSEA in Cergy-Pontoise


Abstract: In this tutorial, the iterative decoding techniques for non-binary LDPC codes will be presented, both from the theoretical aspects of Belief Propagation and its analysis, and from more practical aspects of efficient implementation. In a first part, introduction on error correction coding with LDPC will be presented, and the main differences between iterative BP decoding of binary and non-binary LDPC codes will be highlighted. Then, in a second part, the recent solutions proposed in the literature to reduce the complexity of non-binary decoders, both for memory storage and computational burden reduction, will be presented. Finally, in a third part, some applications where non-binary LDPC codes show their best potential will be discussed.


Bio: David Declercq was born in June 1971. He graduated his PhD in Statistical Signal Processing 1998, from the University of Cergy-Pontoise, France. He is currently full professor at the ENSEA in Cergy-Pontoise, and CTO of Codelucida©, LLC. He is the general secretary of the National GRETSI association, and Senior member of the IEEE. He is currently the recipient of junior position at the “Institut Universitaire de France”.

His research topics lie in digital communications and error-correction coding theory. He worked several years on the particular family of LDPC codes, both from the code and decoder design aspects.

Since 2003, he developed a strong expertise on non-binary LDPC codes and decoders in high order Galois fields GF(q), with q>>2. A large part of his research projects are related to non binary LDPC codes. He mainly investigated two directions: (i) the design of GF(q) LDPC codes for short and moderate lengths, and (ii) the simplification of the iterative decoders for GF(q) LDPC codes with complexity/performance tradeoff constraints.

David Declercq published more than 30 papers in major journals (IEEE-Trans. Commun., IEEE-Trans. Inf. Theo., Commun. Letters, EURASIP JWCN), and more than 90 papers in major conferences in Information and Communication Theory.

“60GHz CMOS Transceiver for (HD) Video Networks” by Robert Wiser

Date: July 16th, 2012

“60GHz CMOS Transceiver for (HD) Video Networks”

by Robert Wiser, Silicon Image, Inc.


Abstract: Creating and maintaining a robust link with the requisite signal-to-noise ratio for high QoS multi-Gb/s communication in the 60-GHz band presents unique challenges. Adaptive beamforming and beamsteering is the key enabler that helps overcome high path loss and support NLOS operation by finding and maintaining the link with the best system performance. Implementation of these mechanisms requires co-design of the circuits, antenna array, devices, and system algorithms. This presentation focuses on the design of these elements for a chipset supporting high throughput NLOS communication enabling wireless high-definition video.


Bio: Robert Wiser received the B.S.E. and M.S.E. degrees in electrical engineering from Case Western Reserve University of Cleveland, OH in 2002, and the Ph.D. degree in electrical engineering from Stanford University in 2008. While at Case Western Reserve University, his research focused on the fabrication and testing of silicon carbide MEMS resonators. At Stanford he investigated RF filtering with CMOS technologies. He has been with SiBEAM, now the Wireless Division of Silicon Image, since July 2008, designing RF and mm-wave integrated circuits.

“2D to 3D MOS Technology Evolution for Circuit Designers” by Alvin Loke

Date: September 12th, 2012

“2D to 3D MOS Technology Evolution for Circuit Designers”

by Alvin Loke, AMD Inc.


Abstract: Despite increasing economic and technical challenges to scale CMOS, we continue to witness unprecedented performance with 22-nm fully-depleted tri-gate devices now in production. This tutorial offers a summary of how CMOS device technology has progressed over the past two decades. We will review MOS device and short-channel fundamentals to motivate how device architectures in production have evolved to incorporate elements such as halos and spacers, mechanical strain engineering, high-K dielectric and metal gate, and fully-depleted fins. We will also examine key process technologies that have enabled the fabrication of these devices.


Bio: Alvin Loke (S’89-M’99-SM’04) received the BASc (Eng. Physics) degree with highest honors from the University of British Columbia in 1992, and the MSEE and PhDEE degrees from Stanford University in 1994 and 1999 respectively. He was recipient of the UBC Chancellor Entrance and Canadian NSERC 1967 Graduate Scholarships. While at Stanford, his research focused on copper interconnects with low-K polymer dielectric. He has interned at Texas Instruments, Motorola, and at Sumitomo Electric Industries. From 1998 to 2001, he worked on CMOS technology integration at HP Labs, Palo Alto, CA and then at Chartered Semiconductor Manufacturing, Singapore as an Agilent assignee. In 2001, he transferred to Fort Collins, CO, where he designed CMOS phase-locked loop circuits for low-jitter embedded SerDes I/O and ASIC core clocking.

In 2006, he joined Advanced Micro Devices where he is currently a Principal Member of Technical Staff designing high-speed links and addressing analog/mixed-signal concerns for next generation CMOS. Dr. Loke has authored 38 publications and holds 12 US patents. He presently serves on the CICC technical program committee, SSCS Chapters committee, and ECE Department Industrial Advisory Board at Colorado State University. He is presently the SSCS Webinar Taskforce Chair, a Guest Editor for the IEEE Journal of Solid-State Circuits, and a SSCS Distinguished Lecturer.

“Joint IEEE Comsoc – CAS Weekend Workshop: Next Generation Circuit & Systems, Communication and Sensor Technologies in Mobile Devices”

Date: September 29th, 2012

“IEEE Comsoc – CAS Weekend Workshop: Next Generation Circuit & Systems, Communication and Sensor Technologies in Mobile Devices”


Abstract: This workshop covers advances in MEMs based sensors and the continuing progress in the integration of these sensors with control, signal processing and communication electronics. Several of the speakers will also address end user solutions (motion characterization, contextual awareness, gestures, sensor-aided navigation, haptic feedback, health and fitness, life-logging, etc.) which illustrate what can be achieved with the availability of these sensing interfaces (Accelerometer, Proximity, Touch, Pressure, Camera etc) on a connected platform.

After a keynote talk by Professor Tom Lee on the history of wireless communications, we will have two tracks. The first track focuses on progress in the development of circuits, sensors and devices whereas the second track covers advances in hardware and identifies applications/usage scenarios. Each track has approximately a 2 hours and 10min duration including keynotes and Q&A. The attendees will also have an opportunity to interact with vendors at the table-top exhibits. Additionally, attendees may review projects from Santa Clara University’s Center for Science, Technology, & Society at this workshop.


Presentations’ Abstracts

Opening Keynote by Prof. Tom Lee, DARPA MTO Director, on leave of absence from Stanford University

As an antidote to the idea that history progresses linearly, this talk will look at technologies and circuits — many long forgotten – that ultimately led to today’s wireless world. We’ll start with the spark, the arc and the heterodyne, all of which represented the state of the art around the first World War. From there we’ll visit the Neutrodyne TRF receiver on the way to the superhet (through the All-American Five) and the modern era. If time permits, the talk will conclude with wild speculations about the future of wireless.


Morning Track Keynote by Prof. Roger Howe, Stanford University

Micro and nano-fabricated sensors (e.g., accelerometers, gyroscopes, and resonators) and actuators (e.g., light valves for projection and cell-phone displays) are commonplace. In this talk, Prof. Howe will briefly review decades of efforts to co-fabricate NEMS and CMOS, to provide the background for introducing a new logic device: the nanoelectromechanical (NEM) relay. At Stanford, Prof. How’s group has developed a fabrication process for integrating a lateral (in-plane) electrostatic relay. Early in the project, a system application for NEM relays was identified – implementing the programmable routing for FPGAs. Prof. Howe will review the fabrication challenges, contact physics, and the potential post-CMOS integration of NEM relays.

Many NEMS require hermetically sealed, low-pressure ambients, a need that motivated the development of low-cost, wafer-scale vacuum encapsulation technologies. Over the past several years, Prof. Howe’s group and others at Stanford have been exploring applications that leverage wafer-level vacuum: thermionic energy conversion and vacuum cavity THz sources. Thermionic energy converters were conceived in 1915, demonstrated in 1939, and were the focus of astronomical investments during the space race by NASA and the Soviet Union. These devices, which achieved 15% efficiency, are suitable for wafer-scale processing, using high-temperature materials developed for harsh-environment sensors and other applications. Prof. Howe will review the current state of wafer-scale thermionic converters and potential applications to microcogeneration and concentrated solar power. Thermionic emitters are also useful for electron injection – an essential component a wafer-scale vacuum cavity oscillator. These devices have attractive characteristics for efficient generation of power in the THz frequency range.


Event-based analog sensing by Theodore Yu, PhD, Texas Instruments

Presentation available in pdf

The event-based sensing approach encodes features of interest from the environment or scene into events. Incorporation of low-power analog signal processing locally near the sensor seeks to reduce the amount of redundant data processed in the system. Furthermore, encoding of relevant features into time-stamped events allows for additional signal processing techniques that naturally exploit the temporal dynamics of the sensed information. Dr. Yu will first present some work that implements event-based sensing techniques for visual and acoustic sensors. The second part, he will cover the design and implementation of an event-based processor modeled after the dynamics of the brain. Within this architecture Dr. Yu will demonstrate spike- based event-driven coincidence detection in neural synchrony with applications towards temporal encoding and decoding of scenes.


Progress in Extreme Environmental Sensing Using Wide Bandgap Semiconductor Thin Films by Prof. Debbie G. Senesky, Stanford University

In this presentation, Prof. Senesky will discuss the synthesis of temperature tolerant, chemically resistant, and radiation-hardened wide bandgap semiconductor thin films and nanostructures. These new material sets serve as a platform for the realization of sensor, actuator, and electronic components that can operate and collect data under the most hostile conditions. More specifically, smart and adaptable structures for extreme environments are enabled through the technology developed in her laboratory. Her research efforts support a variety of applications including deep space systems, hypersonic aircrafts, combustion monitoring and subsurface monitoring.


CMOS-MEMS integration will be a requirement for the next generation “smart” MEMS sensors by Stephen Lloyd, VP of Engineering, InvenSense

Presentation available in pdf

In years past, many of the attempts at CMOS-MEMS integration have had marginal results. Consequently, many of today’s leading high volume MEMS suppliers use separate MEMS and CMOS processes and leverage advanced packaging to combine the two die into a single package. There are significant challenges in combining MEMS with CMOS, yet once these challenges are overcome, a CMOS-MEMS platform offers a significant advantage for implementing highly integrated “smart” sensors. Verified by the evolution of CMOS technology, integration is an extremely powerful tool to lower overall solution cost and power. CMOS-MEMS integration achieves similar significant advantages in cost, size, and power consumption over solutions with separate MEMS and CMOS. This discussion will cover the challenges of CMOS-MEMS integration and demonstrate how effective solutions to these challenges exist and are in high-volume production today. We will discuss the advantages of a CMOS-MEMS platform for many applications such as inertial, audio, ultra- sonic, timing, RF, biological, chemical and gas sensing. The talk will also briefly cover a CMOS-MEMS platform that is available via a fabless design model (NF Shuttle) where silicon is manufactured at leading foundries.


Emerging Multi-sensor Modules and Sensor Fusion Enables New Applications by Jay Esfandyari, MEMS Market Development Manager, STMicroelectronics

MEMS based sensors hold a distinct edge over other technologies in performance, size, cost and current consumption. These advantages have enabled the strong penetration of MEMS sensors into high growth applications in portable devices.

Multi-sensor based applications such as indoor navigation, motion gaming, robot balancing, image stabilization, air mouse, human body tracking and unmanned aerial vehicles, etc. require the fusion of the data of these sensors to achieve high performance and short response time.

This presentation will give an overview of which sensors are used in sensor fusion, what the major technical parameters are required and what the most popular applications of the sensor fusion solution are. It will also discuss the challenges the developers are facing and the limitations associated with the sensor fusion implementation.


Introducing World’s first Piezoelectric MEMS Oscillators by Harmeet Bhugra, Managing Director, MEMS Group, Integrated Device Technology, Inc.

Presentation available in pdf

Mr. Bhugra will discuss the introduction of world’s first high performance piezoelectric MEMS oscillators. These non-quartz oscillators are gradually penetrating the $4B frequency reference marketplace and are increasingly being favored by system designers. He will discuss major application trends and address why alternative solutions to quartz are gaining traction. He will also discuss what it takes to get a MEMS product from paper to production including key lessons learned during development.


Sensor technologies leading a convergence of human interface and product differentiation by Ian Olsen, Executive Director, Optical Sensor Business, Maxim Integrated Products, Inc.

Presentation available in pdf

The industry and ultimately consumers are at a technology cross road. Applications running on mobile appliances have become the driving force behind consumers thirst for newer platforms. Rich sensory enabled devices enable more compelling apps and thus OEM’s are reaching out to find and integrate new sensor technology. Simultaneously, sophisticated graphics and multi core engines in these same appliances are enabling the next revolutionary step in human interface.. one of gestures and emersion media. So compelling are these two trends that they have now become the mainstream of today’s movies and technology demonstration. This is the new tricorder, the new paradigm of mobile and consumer electronics.


Hardware Design and Software Development Challenges in the Integration of Sensors in to End Products by Samyeer Metrani, VP of Design Services, Mistral Solutions Inc.

Presentation available in pdf

Accelerometers, digital compass, gyroscopes, compasses, GPS, ambient light sensors (ALS), etc., have become standard capabilities in most mobile devices. These devices, along with cameras, microphones etc. are helping OEM’s to build high end solutions like augmented reality, etc., while also improving portability, mobility and lightweight design battery-operated mobile devices. The integration of multiple degrees of freedom (nDOF) sensors into a mobile device presents challenges in power management, thermal dissipation, control, filtering and sensory output and its correlation and fusion, to list a few. The presentation discusses the design requirements and features to be considered when integrating MEMS sensory components in custom mobile hardware and some of the software architecture requirements of integrating them into operating systems like iOS, Android and Windows CE.

“RF Mixers: Analysis and Design Trade-offs” by Hooman Darabi

Date: November 10th, 2012

“RF Mixers: Analysis and Design Trade-offs”

by Hooman Darabi, Broadcom Corp.


Abstract: Mixers are essential building blocks of every RF transceiver, often compromising the noise and linearity performance of the entire receive or transmit chain. In this short course various mixer architectures such as passive vs. active, current-mode vs. voltage-mode, and their properties are analyzed and discussed. Of special importance, is the noise response of the mixers which is not very well understood due to the nonlinear and time variant nature of the block. We will focus on intuitive and qualitative ways of analyzing the noise of both passive and active mixers. More advanced topics such as 25% vs. 50% duty cycle design trade-offs, low/high side gain imbalance in complex receivers, as well as effects of noise and nonlinearity folding in both receivers and transmitters are discussed.


Bio: Hooman Darabi received the BS and MS degrees both in Electrical Engineering from Sharif University of Technology, Tehran, Iran, in 1994, and 1996 respectively. He received the Ph.D. degree in electrical engineering from the University of California, Los Angeles, in 1999. He is currently a Sr. Technical Director and a Fellow with Broadcom Corporation, Irvine, CA, as a part of mobile and wireless group. His interests include analog and RF IC design for wireless communications. Hooman is an IEEE distinguished lecturer.

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