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2013 Events


“Advanced EDA Tools for Multi-Radio High-Frequency Accurate IC Design” by Yasser Hussein

Date: January 28th, 2013

“Advanced EDA Tools for Multi-Radio High-Frequency Accurate IC Design”

by Yasser Hussein, PedaSoft

 

Presentation available in pdf

Abstract: Advances in technology have enabled the possibilities to integrate multi-band and multi-mode radios into single packaged chips covering the diversity of communication standards from 2G GSM, 3G UMTS, to 4G LTE and LTE-advanced as well as WLAN, BT, and GPS impart unique challenges on the RF CAD/EDA due to the high complexity and integration of such chips. Existing EDA tools to model/simulate RF-chip performance, model the active and passive components separately. Subsequently, the designer uses simple calculations (or co-simulation) to approximate the performance of the overall RF design. Such calculations or methodologies were somewhat effective in the past but result in grossly inaccurate results for today’s complex chips. The consequence is excessive design cycles (typically 3 to 4), high costs and ultimately lost time-to-market opportunities. For today’s complex chips, a designer needs to simulation the IC package as a whole to include electromagnetic coupling, interference, and radiation.

The focus in this talk will be on the challenges and requirements as well as the latest trends on multi-radio EDA. A thorough discussion of advanced techniques for receivers and transmitters modeling of multi-radio SoC/SiP will be presented.

 

Bio: Dr. Yasser Hussein received a Ph.D. in Electrical Engineering from Arizona State University, Tempe, AZ in 2003. From 2003 to 2006, he was a Member of Research Staff at Stanford University’s SLAC. During the spring of 2005, he was a Lecturer with the Electrical Engineering Department, Stanford University, where he developed and lectured a new course concerning advances in RF modeling and design. From 2005 to 2007, he led the RF design team and was the principle technical contributor for Intel’s Wireless Laminate Module (WLM) technology and product development that integrated the radio, including the power amplifier, and the base band in a single packaged laminate module for the first time at Intel. In 2007, he joined PedaSoft, a start-up company, where he is now the Chief Technology Officer.

Dr. Hussein is an IEEE Senior Member, nominated member for the US National Committee of the International Union of Radio Science (USNC-URSI), nominated member for Sigma Xi, Listed in Who’s Who in America, reviewer for several journals including IEEE Transactions on Microwave Theory and Techniques, Antennas and Propagations, Microwave Magazine, and Magnetics. He has a book chapter on advanced RF design and more than 25 lead-author publications in refereed Journals and conference proceedings, as well as a patent pending at USPO. He has been a speaker for more than 40 talks on advanced RF design including invited talks at Intel, Analog Devices, Sigrity, Skyworks, Triquint, Jet Propulsion Laboratory (JPL-Caltech.), and several IEEE societies (MTT-S & AP-S) including Santa Clara and Silicon Valley Chapters, and MTT Symposia.


“Continuous-time Delta Sigma Modulators with Improved Linearity and Reduced Clock Jitter Sensitivity using the Switched-Capacitor Return-to-Zero (SCRZ) DAC” by Prof. Shanthi Pavan

Date: March 11th, 2013

“Continuous-time Delta Sigma Modulators with Improved Linearity and Reduced Clock Jitter Sensitivity using the Switched-Capacitor Return-to-Zero (SCRZ) DAC”

by Prof. Shanthi Pavan, IIT-Madras

 

Presentation available in pdf

Abstract: Conventional continuous-time modulators that use non-return-to-zero (NRZ) feedback DACs suffer from distortion due to inter-symbol-interference (ISI) and are sensitive to clock jitter. Using a return-to-zero (RZ) DAC solves the problem of ISI, but exacerbates clock jitter sensitivity. The clock jitter sensitivity of an NRZ DAC can be reduced using a switched-capacitor (SC) DAC, but the large peak-to-average ratio of the DAC waveform degrades modulator linearity. In this work, we introduce the Switched-Capacitor Return-to-Zero (SCRZ) DAC, which combines the low clock jitter sensitivity of the SC DAC with the low distortion of an RZ DAC.  Measured results  from a test chip fabricated in 0.18um CMOS demonstrate the efficacy of the SCRZ technique.

 

Bio: Shanthi Pavan obtained the B.Tech degree in Electronics and Communication Engineering from the Indian Institute of Technology, Madras in 1995 and the M.S and Sc.D degrees from Columbia University, New York in 1997 and 1999 respectively.  After working in industry for a few years, he moved to the Indian Institute of Technology-Madras, where he is now a Professor of Electrical Engineering. His research interests are in the areas of high speed analog circuit design, sensing and signal processing.

Dr.Pavan is the recipient of  several awards, including the IEEE Circuits and Systems Society Darlington Best Paper Award (2009). He is the  Deputy Editor in Chief  of the IEEE Transactions on Circuits and Systems: Part I – Regular Papers and serves on the Data Converter Committee of the International Solid State Circuits Conference (ISSCC).


Technical Talks on High Speed ADCs

Date: April 22nd, 2013

Event co-sponsored by the
IEEE Solid-State Circuits Society (SSCS) SCV Chapter

First Talk:

A 10.3GS/s 6b Flash ADC for 10G Ethernet Applications
by Shwetabh Verma, Broadcom Corporation

Paper and presentation available here (IEEEXplore subscription required)

Abstract: A 40-nm CMOS 10-GS/s, 6-bit Flash ADC has been designed for
a DSP-based receiver which meets the requirements for all NRZ 10G
Ethernet standards. The ADC uses both conventional comparator
calibration and redundancy to reduce power. The micro-architecture
enables dynamic reconfiguration of the comparator order – reducing the
required comparator offset adjustment range during ADC calibration.
The ADC occupies 0.27mm2 and consumes 240mW.

Bio: Shwetabh Verma received the BS degree from the University of
Toronto in 1998, and the MS and PhD degrees from Stanford University
in 2000 and 2005 respectively. His graduate work focused on the design
of low-cost, low-power technology for wireless personal area networks.
Since 2005 he has been employed at Aeluros Inc., now part of Broadcom,
designing circuits and systems for broadband data communications.

 

Second Talk

A 14b 2.5GS/s 8-Way Interleaved Pipelined ADC With Background Calibration and Digital Dynamic Linearity Correction
by Brian Setterberg, Agilent Technologies

Paper and presentation available here (IEEEXplore subscription required)

Abstract: Eight 14 bit pipelined ADCs are time interleaved to provide
an aggregate 2.5 GS/s conversion rate. The interleaved architecture
enables a metastable error rate below 1E-17 to meet the stringent
requirements of test and measurement applications. Continuous
background calibration and digital dynamic linearity correction enable
the interleaved architecture to achieve 78 dB SFDR over a signal
bandwidth of more than 1 GHz.

Bio: Brian Setterberg holds a Bachelor of Science degree in electrical
engineering from Washington State University and a Master of Science
degree in electrical engineering from Stanford University. He joined
Hewlett Packard Laboratories in 1997 to develop mixed-signal
integrated circuits for radio applications. He is currently with
Agilent Research Laboratories, where his recent work has been focused
on high performance analog to digital converters optimized for test
and measurement systems.

 


Technical Talks on Wideband Power Amplifier Linearization

Date: May 13th, 2013

First Talk:

RF Pre-Distortion to Linearize Wireless Broadband Power Amplifiers
by Rajeev Krishnamoorthy, Scintera Networks

Presentation available to download here: pdf

Abstract: Power amplifiers in wireless communication systems are required to be both linear and efficient, and pre-distortion techniques to achieve high efficiency with good linearity are widely used. The techniques are generally baseband digital solutions, but recently a novel analog predistortion technology which operates on signals in the RF domain has been gaining traction. This talk will cover this technology as well as the family of RF Power Amplifier Linearizers (RFPAL) System-on-Chip (SoC) solutions from Scintera. Due to the low power consumption of these ICs, this method of linearization is becoming especially popular for mid-to-low power cellular base stations as well as several other adjacent markets. We will also discuss the applicability of the underlying analog/RF signal processing technology to other markets.

Bio: Rajeev Krishnamoorthy is CTO of Scintera Networks. Prior to this, he was founder and CEO of TZero Technologies (acquired by NDS Surgical Imaging), a fabless semiconductor company providing high-performance Ultra Wideband chipsets and digital video solutions. Before founding TZero, Rajeev was VP, Technology at Iospan Wireless (later part of Intel) and helped develop the first commercially available MIMO cellular wireless systems. He began his career at Bell Labs conducting research in communications and data networking, and in the wireless LAN division of AT&T/Lucent in the Netherlands where he played a key role in the development of the earliest 802.11 and 11(b) (WiFi) products which enabled the first widely deployed wireless LAN networks.
Rajeev has been an EIR and consultant at Globespan Capital Partners and Tallwood Venture Capital, an advisor and board member of several venture-backed startups, and a Consulting Professor at Stanford University. He earned his PhD from Cornell and his BS from Caltech.

Second Talk:

A 200mW 100MHz-to-4GHz 11th-Order Complex Analog Memory Polynomial Predistorter for Wireless Infra-structure RF Amplifiers
by Frédéric Roger, Scintera Networks

Paper and presentation available here (IEEEXplore subscription required)

Abstract: We present a fully integrated, 11th order, 4-memory terms, temperature compensated complex analog predistorter. It is implemented in 0.18um CMOS, does not require any calibration and offers up to 25dB linearity improvement. It occupies 4mm2, consumes less than 200mW from 1.8V, and integrates the whole RFdatapath.

Bio: Frédéric Roger received the Ingénieur degree from ESIEE, Paris, France, in 1996.He was a Research Engineer at Collège de France (CNRS), Paris, from 1996 to 1999, where heworked on data acquisition electronics used in particle physics experiments. In 1999, hejoined Infineon, Munich, Germany, to work on GSM ICs. From 2001 to 2006, he was with Xignal, Munich, where he worked on VDSL, 10-Gb/s ICs, and SONET timing devices.Since 2007, he has been with Scintera,CA, where he is the director of Analog Design. His current work focuses on RF and analog signal processing circuits for PA Linearization.

 


“Chip Design and System Building Techniques at the Interface: Enabling New Wireless Sensors” by Prof. Brian Otis

Date: June 10th, 2013

“Chip Design and System Building Techniques at the Interface: Enabling New Wireless Sensors”

by Prof. Brian Otis, University of Washington

 

Abstract: Advances in chip and system design will help define the next generation of wireless sensors. I’ll discuss examples of our work that have enabled new collaborative science. We will then cover chip design techniques for body-worn/implantable systems and wireless sensors. Finally, I’ll present examples of future mainstream constantly connected devices for improving healthcare. These areas present tough unsolved problems at the interface between the IC and the outside world that cannot be solved by transistor technology scaling alone. Several future applications will demand thin-film realization and biocompatibility of complex systems.  Novel power sources, microscale resonator technologies, and new system integration techniques will be enabling technologies for these emerging systems.

 

Bio: Brian Otis received the B.S. degree in electrical engineering from the University of Washington, Seattle, and the M.S. & Ph.D. degrees in electrical engineering from UC Berkeley. He is an Associate Professor of Electrical Engineering at the University of Washington and holds a position at Google, Inc.  His research interests are low power chip design, micromechanical resonator based clocks, and wireless bioelectrical interface circuits and systems.


What Every Electrical Engineer Should Know about Nonlinear Circuits and Systems – CAS DLP Presentation

Date: August 5th, 2013

Presentation available to download here: pdf
 
Special Event Details:
  • Time: Doors open at 6pm, presentation will start at 6.30pm
  • Cost: Free, however a $5 food donation will be accepted at the door
  • Length: This will be a 2 hour presentation (with a 15 min break)

Speaker: Prof. Michael Peter Kennedy, CAS Distinguished Lecturer

Department of Electrical & Electronic Engineering, University College Cork, Ireland and Tyndall National Institute, Cork, Ireland

Abstract: The theory of Circuits and Systems lies at the core of Electrical & Electronic Engineering education. Traditionally, training in circuits and systems has emphasized linear concepts and has focused almost exclusively on linear analysis and synthesis techniques. While these are invaluable in practice, engineers should be aware of the limitations of linear methods. Many common circuits and systems rely on nonlinear effects; their behavior simply cannot be explained using linear methods. A basic understanding of nonlinear circuits and systems can provide useful insights.

This presentation introduces key concepts in Nonlinear Circuits and Systems using examples from Electrical & Electronic Engineering.

Bio: Michael Peter Kennedy is Professor of Microelectronic Engineering at University College Cork (UCC).  He received the BE (Electronics) degree from UCD in 1984, the MS and PhD from the University of California at Berkeley in 1987 and 1991, respectively, and the DEng from the National University of Ireland in 2010. He joined UCC as Chair of the Department of Microelectronic Engineering in 2000. He served as Dean of the Faculty of Engineering from 2003 through 2005 and as Vice-President for Research from 2005 to 2011.  He has over 330 research publications (including four patents) in the fields of oscillator design, hysteresis, neural networks, nonlinear dynamics, chaos communication, mixed-signal test, and frequency synthesis. He has worked as a consultant for SMEs and multinationals in the microelectronics industry and is founding Director of the Microelectronics Industry Design Association (MIDAS Ireland) and the Microelectronic Circuits Centre of Ireland (MCCI).He was made a Fellow of the Institute of Electrical and Electronic Engineers (IEEE) in 1998 for contributions to the theory of neural networks and nonlinear dynamics and for leadership in nonlinear circuits research and education. He has received many prestigious awards including Best Paper (International Journal of Circuit Theory and Applications), the 88th IEE Kelvin Lecture, IEEE Millenium and Golden Jubilee Medals, the inaugural Royal Irish Academy Parsons Award in Engineering Sciences, and the IEEE Solid-State Circuits Society Chapter of the Year Award 2010.  In 2004, he was elected to membership of the Royal Irish Academy and was made a Fellow of the Institution of Engineers of Ireland by Presidential Invitation. From 2005 to 2007, he was President of the European Circuits Society and Vice-President of the IEEE Circuits and Systems Society (with responsibility for Europe, Africa and the Middle East). In 2012, he was appointed as a Distinguished Lecturer of the IEEE CAS Society and was elected Secretary for International Relations of the Royal Irish Academy.


Circuits and Systems For Wearable and Implantable Medical Devices – CAS DLP Presentation

Date: September 16th, 2013

Speaker: Prof. Wouter A. Serdijn, CAS Distinguished Lecturer, Head Biomedical Electronics Laboratory, Delft University of Technology, The Netherlands

Presentation available to download here: pdf

Abstract

In the design process of wearable and implantable medical devices (IMDs), such as hearing instruments, pacemakers, cochlear implants and neurostimulators, the tradeoff between performance and power consumption is a delicate balancing act. In this presentation I will cover techniques to deal with the acquisition and generation of electrophysiological signals and to provide reliable communication with and through the body. We will discuss signal-specific analog-to-digital converters, morphological filters, arbitrary-waveform neurostimulators, energy harvesting and ultra wideband wireless communication from a low-power circuits and system perspective. Design examples and their performance will be discussed in detail.

Bio
Wouter A. Serdijn received the Ingenieur’s (M.Sc.) degree (cum laude) in Electrical Engineering from Delft University of Technology, The Netherlands, in 1989. Subsequently, he joined the Electronics Research Laboratory of the same university where he received his Ph.D. in 1994.His research interests include low-voltage, ultra-low-power and ultra wideband analog integrated circuits for wireless communications, pacemakers, cochlear implants, portable, wearable, implantable and injectable ExG recorders and neurostimulators. In this field he co-authored 8 books, 6 book chapters and more than 250 scientific publications and presentations.He has been supervising 25 Ph.D. students, 87 M.Sc. students and 19 B.Sc. students. He received the Electrical Engineering Best Teacher Award in 2001 and 2004. He has served, a.o., as Technical Program Chair for IEEE BioCAS 2010 and as Technical Program Chair for IEEE ISCAS 2010 and 2012, as a member of the Board of Governors (BoG) of the IEEE Circuits and Systems Society (2006—2011) and as Editor-in-Chief for IEEE Transactions on Circuits and Systems—I: Regular Papers (2010—2011). He will be General Co-Chair for IEEE BioCAS 2013, TPC  Co-Chair for IEEE ISCAS 2014 and General Co-Chair for IEEE ISCAS 2015.Wouter A. Serdijn is an IEEE Fellow, an IEEE Distinguished Lecturer and an IEEE mentor.

Sign-based Zero-Forcing Adaptive Equalizer Control for High-Speed I/O

Date: November 18th, 2013

Event sponsored by IPC      IPC APEX logo

 

Speaker: Dr. Yasuo Hidaka, Fujitsu Laboratories of America

Presentation available to download here: pdf

Abstract

Equalizers are often used for wireline transceivers to cancel Inter-Symbol Interference (ISI) caused by frequency-dependent channel loss. Adaptation of equalizer parameters is desired, because channel characteristics are generally unknown. Least Mean Square (LMS) and Sign-Sign-LMS (SS-LMS) are adaptation algorithms widely used in digital signal processing, because it is easy to achieve minimum mean square error (MMSE) using these algorithms. However, LMS and SS-LMS are generally not applicable to mixed-signal circuits such as continuous-time linear equalizer (CTLE) or transmitter pre-emphasis in High-Speed I/O, because key reference information required for LMS and SS-LMS are not necessarily available for those mixed-signal circuits. On the other hand, Sign-based Zero-Forcing (S-ZF) is an adaptation algorithm that is always applicable to mixed-signal circuits including CTLE and transmitter pre-emphasis, because it does not require any additional reference information in analog circuits other than error information. Unlike conventional ZF, LMS, or SS-LMS, S-ZF does not assume random data sequence for measurement of correlation between error and reference information. Instead, S-ZF uses filter patterns to accurately de-convolve error information to residual ISI information. S-ZF works robustly for non-scrambled data such as 8B10B coding which may include a monotone sequence such as continuous 1010. Adaptation performance of S-ZF can be similar to LMS and SS-LMS, if used with proper parameters, because S-ZF can also achieve the MMSE condition for the worst channel. For decision feedback equalizer (DFE), S-ZF converges to the same state as SS-LMS, because they are based on the same formula. We have applied the S-ZF scheme for adaptation of equalizers such as CTLE, speculative or non-speculative DFE, and transmitter pre-emphasis in several generations of high-speed I/O from 1.25Gb/s up to 32Gb/s. Recently, we have also extended the S-ZF scheme to be applicable to low-frequency equalizer for which measurement of long-term residual ISI such as for 50 unit intervals (UIs) is required.


Bio
Dr. Yasuo Hidaka is a senior researcher in Platform Technology Innovation Group at Fujitsu Laboratories of America, Sunnyvale, California. At FLA, he is working on research and development of high-speed interconnect technologies for Fujitsu Servers, primarily focusing on signal integrity problems of electrical interconnect from both sides of transmission channel and I/O circuit. He has acquired a broad range of in-depth experience and knowledge in his career in computer science, electrical engineering, and mechanical engineering, including but not limited to mixed-signal analog circuit, digital/analog signal processing, logic design and verification, high-speed analog circuit, adaptive control theory, etc. He received his Ph.D. in Information Engineering from University of Tokyo in 1995 where his research focused on parallel computer architecture. He received M. Eng. in Information Engineering and B. Eng. in Precision Machinery both from University of Tokyo in 1991 and 1989, respectively. He co-authored 2 books, authored or co-authored 14 journal papers, and 15 peer-reviewed conference papers including 5 papers in ISSCC. He holds 31 granted U.S. patents.
 

 
Event sposored by IPC and IPC APEX EXPO 2014

IPC APEX EXPO 2014 will be held March 25–27 at the Mandalay Bay Convention Center in Las Vegas, Nevada. Connect with thousands of industry professionals from more than 50 countries. Explore advanced and emerging technologies in printed board design and manufacturing, electronics assembly and test. Compare equipment, materials and supplies from more than 400 of the industry’s leading companies. Learn about the latest research and manufacturing processes that will help advance your career and your company. Network with your peers and build relationships with experts from around the world.

 The IPC APEX EXPO technical conference is known worldwide as one of the finest and most selective in the world. More than 100 technical papers and posters on the latest research advancements and innovations will be presented.

 Professional development courses will provide comprehensive updates on a variety of industry topics, including: assembly processes for lead free and tin-lead; quality, test and reliability; cleaning, coating & contamination; PCB design, fabrication and materials; emerging technologies and much more.

 In addition, our keynote speakers, like Dr. Peter Diamandis, Chairman and CEO of X PRIZE Foundation, will surely inspire. Dr. Diamandis will share his insights into how breakthroughs in exponentially growing technologies like artificial intelligence, nanomaterials, 3-D printing, robotics and digital medicine will re-engineer products, companies, industries — and even society — over the next 20 years.

 Mark your calendar now for IPC APEX EXPO 2014, March 25–27 at the Mandalay Bay Convention Center in Las Vegas, Nevada. Learn more at www.IPCAPEXEXPO.org.


Life at the intersection of the smart phone, social computing & gamification: How I lost 80 pounds in 1 year and kept it off

Date: December 9th, 2013

Speaker: Jonathan David, Qualcomm, Inc.

Presentation available to download here: pdf


 

Abstract

There is really no real secret to how to lose weight: eat fewer calories and exercise more. However many of us find that actually making ourselves do this is quite difficult. Using a variation on the methods documented in “the Game-On Diet”, weight loss is possible without pain, deprivation and hunger pangs. If you enjoy beer, you can even have a beer most days. It turns out that the electronics in our pockets today change the game even more. In a less technical, year end presention, Jonathan shares how he leveraged free apps on his always connected smartphone, and a game to make weight loss painless, safe, easy and even fun, highlighting apps you can start using now to make your life better. 

Bio
Jonathan David is a Senior Staff engineer at Qualcomm Atheros where he works on mixed-signal functional verification. He is a Senior Member of the IEEE,  a founding member of the Santa Clara Valley CAS and SSC chapters, and past Chair of the Santa Clara Valley IEEE Section. He likes hiking, especially in the bay area hills, cycling, reading science fiction,  & discussions with friends over great craft beer.

Development of Graphene-Based RF Integrated Circuits

Date: December 12th, 2013

Speaker: Dr. Alberto Valdes-Garcia, IBM T. J. Watson Research Center

Event co-sponsored by IEEE SCV SSCS


 

Abstract

Graphene is a two-dimensional (2D) material, consisting of a sheet of carbon atoms arranged in a honeycomb lattice, and possesses exciting potential for high frequency electronics due to its high intrinsic carrier mobility (> 10,000 cm2/Vs at room temperature) and large saturation velocity (~ 5.5´107 cm/s), both of which greatly exceed the corresponding values in silicon. The potential of any new material to make a significant impact into the modern world of microelectronics is contingent on its ability to achieve scalable integration into practical circuits. After the successful demonstration of graphene devices with cut-off frequencies in the GHz-range, the next major step to move graphene technology forward into the practical domain of RF electronics is to address the challenges associated with circuit integration. This presentation summarizes the recent development and characterization of graphene-based RF devices and integrated circuits. The first wafer-scale process developed for graphene RFIC integration on SiC wafers is discussed along with the design and measurements of a 5-GHz down-conversion mixer.  Next, a frequency doubler fabricated on CVD graphene is presented as a proof-of-concept ofgraphene-based circuits in a 200mm platform. Finally, some of the special properties if these ICs (such as their low sensitivity to temperature variations), and the remaining challenges for graphene RFIC technology will be discussed.

Bio
Alberto Valdes-Garcia is currently a Research Staff Member and Manager of the RF Circuits and Systems Group at the IBM T. J. Watson Research Center. He received the Ph.D. degree in Electrical Engineering from Texas A&M University in 2006. His present work is on silicon-integrated millimeter-wave systems and carbon electronics.From 2006 to 2009, Dr. Valdes-Garcia served in the IEEE 802.15.3c 60GHz standardization committee. Since 2009 he serves as Technical Advisory Board member with Semiconductor Research Corporation (SRC), where he was Chair of the Integrated Circuits and Systems Sciences Coordinating Committee in 2011 and 2012. In spring 2013 he was also an Adjunct Assistant Professor at Columbia University. He holds 8 issued US patents with 25+ pending. His scholarly work (65+ authored or co-authored publications) has already received more than 1300+ independent citations in indexed journals. He is a co-Editor of the book 60GHz technology for Gbps WLAN and WPAN: From Theory to Practice (Wiley, 20011).Dr. Valdes-Garcia is the winner of the 2005 Best Doctoral Thesis Award presented by the IEEE Test Technology Technical Council (TTTC), the recipient of the 2007 National Youth Award for Outstanding Academic Achievements, presented by the President of Mexico, and a co-recipient of the 2010 George Smith Award presented by the IEEE Electron Devices Society. In 2013, he was selected by the National Academy of Engineering for its Frontiers of Engineering Symposium.

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