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Date: September 21st, 2018
IEEE Circuits and Systems Society-Silicon Valley (CAS-SV) Artificial Intelligent For Industry Forum



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2016 Events

Physical Foundations of Green Communications Systems

Date: January 11th, 2016

Co-sponsored by IEEE SCV COMSOC

LocationQualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA

Time: 6:30pm-9pm

Registration Cost: Free. Click Here to RegisterFood donation accepted: $2 for IEEE member, $5 for non-IEEE member

Speaker: Dr. Earl McCune, RF Communications Consulting, Panasonic Technology Fellow (ret.), IEEE MTT Distinguished Microwave Lecturer 

Presentation available for download here: pdf


Achieving energy-efficient “Green” communications requires the cooperation of all blocks within a communication system.  This includes the digital and analog basebands, the transmitter, the receiver, the protocol, and most importantly the signal modulation selected.  Optimizing any one of these, which is by far the most common approach, leaves the entire system far from its optimum efficiency.  But when the entire system is jointly designed for optimum efficiency in the presence of all  communication throughput requirements, significant energy savings relative to conventional design can be realized.  These techniques hold equally for wireless and wireline communication channels.

This presentation begins with the fundamental physics of total energy efficiency, and discusses the resulting circuit operating aspects necessary to achieve the best available efficiency.  Then the system aspects of modulation properties and protocol are derived that are necessary to allow access to the derived circuit optimal efficiencies.  Collection of all these results into a set of joint optimization parameters is then presented as the fundamental requirements for achieving Green communications systems.

Bio for Earl McCune:

Earl received his Bachelors, Masters, and Doctorate degrees at UC Berkeley, Stanford, and UC Davis respectively.  His experience in RF circuits, signals, and systems goes back more than 40 years.  Within this career he has founded two Silicon Valley startups, the first one doing modulated direct digital frequency synthesis in 1986 which merged with Proxim in 1991.  The second start-up, Tropian, did switch-based RF transmitters from 1996 and was acquired by Panasonic 10 years later.  He retired from Panasonic in 2008 as a Managing Director and Corporate Technology Fellow.  He has 76 issued patents in the USA.  He is a double author with Cambridge University Press, first with Practical Digital Wireless Signals, and also with Dynamic Power Supply Transmitters.  He is an appointed IEEE MTT Distinguished Microwave Lecturer since 2013. Dr. McCune has been an invited speaker at RWS, PA Symposium, WAMICON, ISCAS, WCNC, and ISSCC.  He has served on the CICC technical program committee (TPC) since 2000, and also served on the TPC for RWS and the PA Symposium.  He is a regular reviewer for IEEE Journal of Solid State Circuits, Transactions on Microwave Theory and Techniques, and the Transactions on Circuits and Systems.

BRAINWAY: Cognitive Computer Architecture with Applications in Health Care and Personalized Medicine

Date: March 28th, 2016

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co-sponsored by IEEE SCV SSCS, IEEE SCV CS

Speaker: Prof. Andreas Andreou, The Johns Hopkins University, IEEE Fellow, IEEE CAS Distinguished Lecturer


Since the invention of the integrated circuit -the chip in short- in the 1950’s, the microelectronics industry has seen a remarkable evolution from the centimeter scale devices created by Jack Kilby millimeter scale integrated circuits fabricated by Robert Noyce to today’s 8nm feature size MOS transistors. During this time, not only have exponential improvements been made in the scaling of size and the density of devices, but CAD and workstation technologies have advanced at a similar pace enabling the design of complete truly complex Systems On a Chip (SOC). The advances in the microelectronics industry have also enabled the proliferation of computational fields for bio-informatics, systems biology imaging and multi-scale multi-domain modeling. Semiconductor technology is contributing to the advancement of biotechnology, medicine and health care delivery in ways that it was never envisioned; from scientific grade CMOS imagers to silicon photomultiplier and ion sensing arrays. The stunning convergence of semiconductor technology and life science research is transforming the landscape of the pharmaceutical, biotechnology, and healthcare industries, signaling the arrival of personalized and molecular-level imaging diagnosis and treatment therefore speeding up the pace of scientific discovery, and changing the practice and delivery of patient care. Whether through
tissue and organ imaging, Labs-on-Chip or genome sequences, biotechnology and modern medical diagnostics are generating a staggering amount of data stored in data centers! However, computing in data centers, the engines behind our insatiable desire for global communication, instant connectedness and interaction comes at an economic and environmental cost. Future projected needs in data centers are data intensive applications in Cognitive Computing Technology (CCT). CCT aims at advancing intelligent software and hardware that can process, analyze, and distill knowledge from vast quantities of text, speech, images and biological data ultimately with and as much nuance and depth of understanding as a human would. To meet the scientific demand for future data-intensive CCT for every day mundane tasks such as searching via images to the uttermost serious health care disease diagnosis in personalized medicine [1], we urgently need a new cloud computing paradigm and energy efficient i.e. green technologies.

The BRAINWAY project in my lab is aimed at the design of an energy efficient Cognitive Processor Unit (CogPU) that combines Ultra-Low-Voltage (ULV) circuit techniques with brain inspired chip-multiprocessor network-on-chip (NoC) architecture, fabricated in 3D CMOS technology. The design of the CopPU architecture is based on the recently developed mathematical framework for architecture exploration and optimization [2], where neurons are abstracted as digital arithmetic logic units and communication processors [3]. We estimate, that such highly energy efficient CogPU inference engine will provide an energy efficiency gain of about ×65 by using ULV techniques and massive parallelism, a gain of about ×10 by relying on its SOC 3D DRAM, and a gain of about ×15 by relying on new memory based Bayesian inference computational structures. This yields an aggregate improvement factor in energy efficiency of about ×10000, roughly four to five orders of magnitude with respect to present day state-of-the-art. The first generation silicon for the BRAINWAY architecture was taped out in the Tezzaron 3D CMOS technology. The returned chips from 3D CMOS logic stack have been tested fully functional.

[1] A. G. Andreou, “Johns Hopkins on the chip: microsystems and cognitive machines for sustainable, affordable, personalized medicine and health care (invited paper),” IEEE Electronics Letters (special supplement on semiconductors for personalized medicine), pp. s34–s37, Dec. 2011.
[2] A. S. Cassidy and A. G. Andreou, “Beyond Amdahl’s Law: an objective function that links multiprocessor performance gains to delay and energy,” IEEE Transactions on Computers, vol.
61, no. 8, pp. 1110–1126, Aug. 2012.
[3] A. S. Cassidy, J. Georgiou, and A. G. Andreou, “Design of silicon brains in the nano-CMOS era: spiking neurons, learning synapses and neural architecture optimization,” Neural Networks, pp. 1–28, Jun. 2013.


Andreas G. Andreou is a professor of electrical and computer engineering, computer science and the Whitaker Biomedical Engineering Institute, at Johns Hopkins University. Andreou is the co-founder of the Johns Hopkins University Center for Language and Speech Processing. Research in the Andreou lab is aimed at brain inspired microsystems for sensory information and human language processing. Notable microsystems achievements over the last 25 years, include a contrast sensitive silicon retina, the first CMOS polarization sensitive imager, silicon rods in standard foundry CMOS for single photon detection, hybrid silicon/silicone chip-scale incubator, and a large scale mixed analog/digital associative processor for character recognition. Significant algorithmic research contributions for speech recognition include the vocal tract normalization technique and heteroscedastic linear discriminant analysis, a derivation and generalization of Fisher discriminants in the maximum likelihood framework. In 1996 Andreou was elected as an IEEE Fellow, “for his contribution in energy efficient sensory

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Data Center Subsystem Design Using FPGAs

Date: April 5th, 2016

IEEE SCV CAS is a co-sponsor of this IEEE SCV CS Tech Talk.

David McIntyre


Date: Tuesday, April 5th, 2016
Speaker: David McIntyre
Time: 6:30 PM (PT) Networking/Refreshments,
7:00 PM Presentation.
Location: Cadence / Bldg 10,
2655 Seely Ave, San Jose, CA (map)


This presentation will provide an introduction to some of the latest trends and challenges in compute, storage and networking applications and will address design considerations using programmable FPGA technology when developing supporting solutions.  Hyper-convergence between these three domains requires tight coupling of hardware resources at the functional and logical levels.  The integrity of the components within each subsystem, e.g. evolving memory types can be properly managed through programmable technology.  Applications will be shared to illustrate the performance advantages when using FPGA technology.

Speaker Bio

David McIntyre has twenty years experience in high performance compute, storage and networking applications for data centers.  His consulting company develops successful go-to-market product strategies for clients from startup through established corporations.  He has held management positions at IBM, Fairchild and Altera (now Intel).

Note : The doors close at 7:30 PM

Eventbrite - Data Center Subsystem Design Using FPGAs

Challenges and Opportunities of circuits and systems on Internet of Things

Date: April 20th, 2016

co-sponsored by IEEE SCV CPMT, IEEE SCV CES

Speaker: Yen-Kuang Chen, Ph.D., IEEE Fellow, Principal Engineer at Intel Corporation


This seminar aims to discuss the technical trends and challenges of circuits and systems on Internet of Things.  Rapid advancement of networking technologies together with extreme miniaturization of computing and communication devices enable a host of new and exciting applications and services that connect the physical and the computational worlds.  In the future, digital sensing, communication, and processing capabilities will be ubiquitously embedded into everyday objects, turning them into the Internet of Things (IoT).  In this new paradigm, smart devices will collect data, relay the information or context to each another, and process the information collaboratively using cloud computing and similar technologies.  This paradigm shift creates numerous challenges and opportunities for engineering. For example, in the future, enormous numbers of sensors will be deployed.  The costs of servicing such sensors will be a major concern. It is often almost impossible to replace sensor batteries once they are in the field.  Therefore, one major challenge is low power sensor design, or designs which do not require a battery change over the lifetime of the sensor.  For example, if a sensor is deployed on an animal for tracking purposes, the battery of the sensor should outlive the animal.  This creates a demand for energy-efficient designs. This seminar will discuss the challenges and opportunities of circuits and systems on Internet of Things.



Dr. Yen-Kuang Chen is a Principal Engineer at Intel Corporation. His research areas span from emerging applications that can utilize the true potential of internet of things to computer architecture that can embrace emerging applications. He has 50+ US patents, 20+ pending patent applications, and 85+ technical publications.  He is one of the key contributors to Supplemental Streaming SIMD Extension 3 and Advanced Vector Extension in Intel microprocessors. He has served as a program committee member of 50+ international conferences on Internet of Things, multimedia, video communication, image processing, VLSI circuits and systems, parallel processing, and software optimization. He is a steering committee member of IEEE Internet of Things Journal, the past-chair of Internet of Things special interest group of IEEE Signal Processing Society, and the Editor-in-Chief of IEEE Journal on Emerging and Selected Topics in Circuits and Systems. He received his Ph.D. degree from Princeton University and is an IEEE Fellow.

“Wireless Bioelectronics”

Date: April 21st, 2016

IEEE SCV CAS proudly co-sponsors the following IEEE SCV SSCS technical talk. 

Title: “Wireless Bioelectronics”

Speaker: Prof. Ada Poon, Stanford University

Date: April 21, 2016 (Thursday)
, Networking and refreshments
6:30-8:00pm, Technical Talk

Please register by Tuesday April 19, 2016 for fast check-in processing by Maxim security. Attendees registered after Tuesday, would have to wait for their badges to be issued on the same day.

Location: This event is held at Maxim Integrated Headquarters not at the usual venue at TI

Jack Gifford Event Center at Maxim Integrated Headquarters building A (160 Rio Robles, San Jose, CA 95134)


Miniaturized electronics, when placed inside the body, can wirelessly monitor and modulate internal activity and thus hold promise as a new class of treatments for disorders. The development of such bioelectronic medicines requires wireless interfaces that are tiny and operate deep in a complex electromagnetic environment. In this talk, I will describe a new method for electromagnetic energy transfer that exploits near-field interactions with biological tissue to wirelessly power tiny devices anywhere in the body, including the heart and the brain. I will discuss engineering and experimental challenges to realizing such interfaces, including a pacemaker that is smaller than a grain of rice and a fully internalized neuromodulation platform. These devices can act as bioelectronic medicines, capable of precisely modulating local activity, that may be more effective treatments than drugs, which act globally throughout the body.


Ada was born and raised in Hong Kong. She received her B.Eng degree from the EEE department at the University of Hong Kong and her Ph.D. degree from the EECS department at the University of California at Berkeley in 2004. Upon graduation, she spent one year at Intel as a senior research scientist. Then, she joined her advisor’s startup company, SiBeam Inc., architecting Gigabit wireless transceivers leveraging millimeter-wave and MIMO technologies. After two years in industries, she returned to academic and joined the faculty of the ECE department at the University of Illinois, Urbana-Champaign. Since then, she has changed her research direction from wireless communications to integrated biomedical systems. In 2008, she moved back to California and joined the faculty of the Department of Electrical Engineering at Stanford University. She is a Terman Fellow at Stanford University. She received the Okawa Foundation Research Grant in 2010 and NSF CAREER Award in 2013.

Registration Link:



We look forward to your participation in our next IEEE SCV CAS events. Please feel free to contact us with any questions or comments.


Package Requirements for High-Speed Systems

Date: May 10th, 2016

IEEE SCV CAS is proudly co-sponsoring IEEE/CPMT Lunch Meeting, in the Santa Clara Valley:

    Package Requirements for High-Speed Systems
— Dr. Wendem T. Beyene, Rambus Inc.

Tuesday, May 10, 2016

  • Optional lunch provided ($10 for non-members, $5 for IEEE members/students/unemployed)
  • Registration (and sandwiches/drinks) at 11:30 AM
  • Presentation-only (no cost) at 12:00 PM noon (come at 11:45 AM)
  • Please reserve by the end of May 8, so we can provide the food.
  • We welcome those looking for employment to bring copies of your resume with you. We will have a table set up for you to sit and network with others.


Please register in advance for this event, using our CPMT Chapter’s EventBrite registration site.

You may register yourself, plus others from your company/institution, for this lunch and presentation. Please make anon-line payment for the lunch.

LOCATION: Texas Instruments Building E Conference Center
2900 Semiconductor Dr. (off Kifer Rd), Santa Clara — click map at right.

    As data rates increase rapidly in high speed systems — such as in SerDes and memory systems — to meet the bandwidth growth required by various applications, the electrical performance of packages has become critical. In addition, the role of new emerging 2.5D and 3D IC packaging platforms with ever-increasing system integration requirements have made the role of packaging even more important. The sources of signal loss, noise coupling and discontinuities in packages must be fully understood and minimized when designing packages. At the same time, the design and development of packages have to meet cost, performance, form factor and reliability goals. In this talk we will examine the key electrical characteristics: signal loss, signal crosstalk, return loss, mode conversion, power integrity and other important factors affecting the bandwidth of high-speed systems. These key performance metrics are discussed using measurement results from various package designs.

Speaker Biography:
    Wendem T. Beyene received his B.S. and M.S. degrees in Electrical Engineering from Columbia University, in 1988 and 1991 respectively, and his Ph.D. degree in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign, in 1997. In the past, he was employed by IBM, Hewlett-Packard, and Agilent Technologies. He is currently a technical director at Rambus Inc. where he is responsible for signal and power integrity of multi-gigabit serial and parallel interfaces.

Tutorial on Selected Topics in RF, Analog and Mixed Signal Circuits and Systems

Date: July 20th, 2016

 (Jointly sponsored by IEEE CAS and IEEE SSC Societies and organized by IEEE SCV SSCS and IEEE SCV CAS)

Program Chairs: Dr. Kiran Gunnam and Dr. Vahidfar Vahid

Event Logistics:  Keplin Johansen, Chair, SCS SCV Chapter and Lizhen Zheng, Chair CAS SCV Chapter

For registration questions, please contact through registration site contact email. Please register in advance through our IEEE meeting registration website.   The online registration deadline is noon, July 18th, 2016.

Venue: TI auditorium, Santa Clara

Texas Instruments Silicon Valley Auditorium 2900 Semiconductor Dr., Santa Clara, CA 95051 Directions and Map

The presentation slides can be found here: pdf.   You will need the attendee password to view them.


July 20th

Selected Topics, Part I

(each talk is 1 hour followed by 15 minutes of Q&A)

4pm-4.30pm-Sign-in, pizza, brief Introduction of speakers

4.30pm-5.45pm- Prof. Tom Lee, “Oscillator Phase Noise”

6.00pm-7.15pm- Dr. Nikola Nedovic, Clock and Data Recovery in High-Speed Wireline Communication

7.30pm-8.45pm- Dr. Bhupendra Ahuja, PLLs

8.45pm-9.00pm- event wrap up


July 21st

Selected Topics, Part II

4pm-4.30pm-Sign-in, pizza, brief Introduction of speakers

4.30pm-5.45pm- Prof. Omeed Momeni, “Terahertz and mm-Wave Signal Generation, Synthesis and Amplification: Reaching the Fundamental Limits”

6.00pm-7.15pm- Prof.Boris Murmann,“Equalization and A/D conversion for high-speed links”

7.30pm-8.45pm- Dr. Alireza Shirvani, RF CMOS Power Amplifiers

8.45pm-9.00pm- event wrap up


Course slides will be delivered to registered attendees as e-book 2 days before the course and will be also available on SSCS and CAS websites for the society members.


Event Pricing:

Regular Attendees: $100 (both days); $70 (for any one of the day)

TI attendees: $25 (both days); $15 (for any one of the day)  (to cover the cost of the food); TI company email address is required for registration, check badge at admission.

IEEE members: 10% discount; please sign in with your IEEE web account during the registration to get the discount.

Refund policy: Cancellation has to be requested online by July 15, 9pm. Refund of the original fee minus handling fee $5 will be made by check.

Trends in Broadband Converters and the Quest for the Software Defined System

Date: September 22nd, 2016

IEEE SCV CAS proudly co-sponsors a special technical seminar on Thursday September 22, 2016 by David Roberson from Analog Devices. The title of the talk will be on:

 “Trends in Broadband Converters and the Quest for the Software Defined System”


The concept of a “software defined radio”, “software defined instrument” or any “software defined” system is to move all the signal processing functions into the digital/software domain, thereby making the system highly reconfigurable.   The principle is simple enough, but actually realizing workable systems is challenging, since the performance demands on the data converters can be daunting, not only in bandwidth, but in dynamic range.  This talk will explore some of the progress that has been made over the last 15 years, with perspectives on both the driving applications and how converter technology has advanced in an effort to meet the applications challenges.


David H. Robertson has been with the Data Converter group of Analog Devices since graduating from Dartmouth College in 1985.  He has worked on a wide variety of high speed D/A and A/D converters on complementary bipolar, BiCMOS and CMOS processes.  He has held positions as a Product Engineer, Design Engineer, and Product Line Director and VP of Analog Technology, working with product development teams in the US, Ireland, Korea, Japan, and China.   Dave is presently the Product and Technology Director for ADI’s High Speed Converter group.

Dave holds 15 patents on converter and mixed signal circuits, has participated in two “best panel” International Solid State Circuits Conference evening panel sessions, and was co-author of the paper that received the IEEE Journal of Solid State Circuits 1997 Best Paper Award.  He served on the ISSCC technical program committee from 2000 through 2008, chairing the Analog and Data Converter subcommittees from 2002 to 2008.

Registration Link:

 Date: September 22, 2016 (Thursday)
, Networking and refreshments
6:30-8:00pm, Technical Talk

Please register by Tuesday September 20, 2016 for fast check-in processing by Maxim security.

 Where: This event is held at Maxim Integrated Headquarters 

Jack Gifford Event Center at Maxim Integrated Headquarters building A (160 Rio Robles, San Jose, CA 95134)

Demystifying Linear Time Varying Circuits

Date: October 20th, 2016

IEEE SCV CAS proudly co-sponsors an IEEE SCV SSC distinguished lecturer seminar on Thursday October 20th, 2016 by Shanthi Pavan, IIT-Madras, with the title:

 Demystifying Linear Time Varying Circuits


An analog/mixed-signal designer encounters time varying circuits everywhere – sample-and-holds, chopper stabilised amplifiers, mixers, switched-capacitor amplifiers and filters, discrete and continuous-time delta sigma modulators, N-path filters. The analysis of signals and noise in these circuits is often associated with messy mathematics and algebra.

This talk aims to demystify linear (periodically) time varying circuits. Starting from first principles, intuition behind various aspects of time-varying circuits and systems will be given. This intuition is illustrated with case studies of practical circuits and systems, like chopper-stabilised amplifiers and continuous-time delta-sigma modulators.


Shanthi Pavan obtained the B.Tech degree in Electronics and Communication Engg from the Indian Institute of Technology, Madras in 1995 and the Masters and Doctoral degrees from Columbia University, New York in 1997 and 1999 respectively. He is now with the Indian Institute of Technology-Madras, where he is a Professor of Electrical Engineering. His research interests are in the areas of high speed analog circuit design and signal processing.

Dr. Pavan is the recipient of many awards for teaching and research, including the IEEE Circuits and Systems Society Darlington Best Paper Award and the Shanti Swarup Bhatnagar Award (from the Government of India). He has served as the Editor-in-Chief of the IEEE Transactions on Circuits and Systems: Part I – Regular Papers. He is a Fellow of the Indian National Academy of Engineering.


Registration Link:


Date: October 20, 2016 (Thursday)
, Networking and refreshments
6:30-8:00pm, Technical Talk

Please register by Tuesday October 18, 2016 for fast check-in processing by Maxim security.


Where: This event is held at Maxim Integrated Headquarters not at our usual venue at TI

Jack Gifford Event Center at Maxim Integrated Headquarters building A (160 Rio Robles, San Jose, CA 95134)

Challenges and Design Considerations for High-Efficiency Modern Wireless RFIC Transmitters

Date: November 17th, 2016

IEEE SCV CAS proudly co-sponsors an IEEE SCV SSC distinguished lecturer seminar on Thursday November 17, 2016 by Osama Shanaa, Mediatek Inc with the title:

“Challenges and Design Considerations for High-Efficiency Modern Wireless RFIC Transmitters”


Modern communication systems are rapidly increasing in complexity fueled by high customer demand for data-rich media streaming over the airwaves. With limited, and sometimes fragmented, available spectrum, very complex modulation schemes with relatively high signal bandwidth are used to be able to “pack” such high data contents for wireless streaming. As a result, tremendous pressure is now put on RFIC designers to deliver circuits that can handle such complex modulation and maintain the required high signal integrity while still be power efficient. This talk walks the audience through design challenges and considerations for high-efficiency transmitters and what areas of research are needed to enable and enhance such circuits moving forward. A dual band CMOS digital transmitter supporting WiFi 802.11 a/b/g/n is used as a design example of a potential technique to address some of the highlighted issues.


Osama Shanaa: (IEEE S’94, M’01, SM’03) has been with Mediatek as a Senior RFIC Design Director since 2008, where he is responsible for various CMOS RF SoC developments for both cellular and connectivity. He received his B.Sc. degree in electrical engineering with high honor from University of Jordan in 1992, the MSEE degree from Portland State University in 1996 and the Ph.D. degree in electrical engineering from Stanford University in 2001. Between 1995-2008 he held various IC design positions at Radio Comm. Corp., National Semiconductor, and Maxim Integrated Products, where he lead many successful RF wireless products generating over $2.5B in revenues. Dr. Shanaa is an Adjunct Professor at the University of California at Berkeley where he teaches advanced circuit design classes for wireless communications. He is a Fulbright scholar, a member of the Etta Kappa Nu honor society and is a senior IEEE member. He currently serves on the Technical Program and Steering Committee for the IEEE RFIC Symposium. Dr. Shanaa is a former Associate Editor for the IEEE Transactions on Microwave Theory and Techniques and is currently a Distinguished Lecturer for the IEEE Solid State Circuits Society.

Registration Link: distinguished-lecturer- seminar-challenges-and-design- considerations-for-high- efficiency-modern-tickets- 29006408950

Date: November 17, 2016 (Thursday)
, Networking and refreshments
6:30-8:00pm, Technical Talk

Where: Texas Instruments Auditorium (Building E Visitor Center), 2900 Semiconductor Dr, Santa Clara, CA 95051, Directions.

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