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2018 Events


“50 Years of Computer Architecture: From Mainframe CPUs to DNN TPUs and Open RISC-V”, by Prof. David Patterson

Date: March 15th, 2018

IEEE CAS SCV Chapter is proudly cosponsoring the technical meeting organized by the IEEE SSCS Chapter:

“50 Years of Computer Architecture: From Mainframe CPUs to DNN TPUs and Open RISC-V”

 

Date & Time: Thursday, March 15, 2018, 6:00 PM – 8:00 PM PDT

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Drive, Santa Clara, CA 95051

Directions: TI-BldgE-Auditorium.pdf

Registration Link: (Mandatory) : https://www.eventbrite.com/e/50-years-of-computer-architecture-from-mainframe-cpus-to-dnn-tpus-and-open-risc-v-prof-david-tickets-43815631734

Registration Fee: IEEE SSCS/CS/SPS/CIS members: free
Students – $3 (Register at Door $3)
IEEE (non-Society) members – $7 donation (Register at Door $10)
Non-members – $10 (Register at Door $15)

Abstract:

This talk reviews a half-century of computer architecture: We start with the IBM System 360, which in 1964 introduced the concept of “binary compatibility”. Next, came the idea of the “dominant microprocessor architecture”, for which the early candidate was the Intel 432 which was shortly replaced by the emergency introduction of the Intel 80×86 in 1978. However, for the next 20 years, the Reduced Instruction Set Computers (RISC) became dominant. Then, the Very-Long-Instruction-Word (VLIW) HP/Intel Itanium architecture was heralded as their replacement in 2001, but instead the role was usurped by AMD’s introduction of the 64-bit 80×86. Thus, while the 80×86 dominated the PC-Era, RISCs have led thereafter, currently with 20B shipped annually (versus 0.4B 80x86s). Since the ending of Moore’s Law and Dennard scaling has stalled performance of general-purpose microprocessors, domain-specific computer architectures are the only option left. An early example of this trend introduced by Google in 2015 is the Tensor Processing Unit (TPU) for cloud-based deep neural networking. The widespread agreement about instruction sets has led to the open architecture RISC-V (“RISC Five”), which has been embraced by more than 100 members of the RISC-V Foundation. RISC-V and accelerators like the TPU demark a new renaissance for computer architecture.

 

Bio:

David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1976. He is also a Distinguished Engineer at Google, where he helps with accelerators for machine learning.

Dave’s research style is to identify critical questions for the IT industry and gather inter-disciplinary groups of faculty and graduate students to answer them. The answer is typically embodied in demonstration systems, and these demonstration systems are later mirrored in commercial products. In addition to research impact, these projects train leaders of our field. The best-known projects were Reduced Instruction Set Computers (RISC), Redundant Array of Inexpensive Disks (RAID), and Networks of Workstations (NOW), each of which helped lead to billion dollar industries.

A measure of the success of projects is the list of awards won by Patterson and as his teammates: the C & C Prize, the IEEE von Neumann Medal, the IEEE Johnson Storage Award, the SIGMOD Test of Time award, the ACM-IEEE Eckert-Mauchly Award, and the Katayanagi Prize. He was also elected to both AAAS societies, the National Academy of Engineering, the National Academy of Sciences, the Silicon Valley Engineering Hall of Fame, and to be a Fellow of the Computer History Museum. The full list includes about 35 awards for research, teaching, and service.

In his spare time, he coauthored seven books, including two architecture texts with John Hennessy, who is past President of Stanford University. Patterson also served as Chair of the Computer Science Division at UC Berkeley, Chair of the Computing Research Association, and President of ACM.


“Neuroengineering the Next Decade” by Prof. Dejan Marković, UCLA

Date: April 18th, 2018

The IEEE Santa Clara Valley Circuits and Systems Chapter proudly co-sponsors the IEEE Santa Clara Valley Solid State Circuits Chapter’s Distinguished Lecturer Seminar on Wednesday, April 18, 2018 by Prof. Dejan Marković, UCLA, titled:

“Neuroengineering the Next Decade”

Abstract:                

Brain disease is a growing socioeconomic problem. In the US, chronic pain affects over 100 million people, with over $600B annual cost; Alzheimer’s disease affects 5.4 million people, with the cost of care exceeding sales of Google; another 5 million live with long-term disability as a result of traumatic brain injury, and there are millions with epilepsy. Drug therapy has failed. The development of neuromodulation technology has become a major medical and social priority.

While much progress has been made in generating brain-machine interface and restoring limb movement, it is much more difficult to restore memories, especially declarative memories, or treat network-scale neuropsychiatric indications. Fueled by insights from clinical neuroscience and engineering, I will discuss a leading-edge technology that can make the fulfillment of memory restoration and the treatment of neuropsychiatric symptoms highly likely.

Bio

Dejan Marković is a Professor of Electrical and Computer Engineering at the University of California, Los Angeles. He is also affiliated with UCLA Bioengineering Department, Neuroengineering field. He completed the Ph.D. degree in 2006 at the University of California, Berkeley, for which he was awarded 2007 David J. Sakrison Memorial Prize. His current research is focused on implantable neuromodulation systems, domain-specific compute architectures, embedded systems, and design methodologies. Dr. Marković co-founded Flex Logix Technologies, a semiconductor IP startup, in 2014. He received an NSF CAREER Award in 2009. In 2010, he was a co-recipient of ISSCC Jack Raper Award for Outstanding Technology Directions. Most recently, he received 2014 ISSCC Lewis Winner Award for Outstanding Paper.

Registration Link:  http://sites.ieee.org/scv- sscs/upcoming-events/

The seminar is FREE and donation is accepted for refreshments (FREE SSCS members/$2 IEEE members/$5 non-members, pay online or at the door).
Eventbrite registration is required for everyone to attend the talk.

Date: April 18, 2018 (Wednesday)
6:00-6:30pm
, Networking and refreshments
6:30-8:00pm, Technical Talk

Where: Texas Instruments Auditorium (Building E Visitor Center), 2900 Semiconductor Dr, Santa Clara, CA 95051, Directions and Map (to locate Building E)


“1+1=3:The Power of Groups: From Tiny Chips to Space Super-Structures”, by Prof. Ali Hajimiri

Date: May 17th, 2018

The IEEE Santa Clara Valley Circuits and Systems Chapter proudly co-sponsors the IEEE Santa Clara Valley Solid State Circuits Chapter’s Distinguished Lecturer Seminar on Thursday, May 17, 2018 by Prof. Ali Hajimiri, California Institute of Technology, titled:

“1+1=3:The Power of Groups: From Tiny Chips to Space Super-Structures”

 

Abstract:                
Many of today’s technological marvels have emerged from putting apparently unrelated ideas together and creating something more than the sum of the parts. Silicon integrated chips have come a long way from the days of first transistors. Nowadays, we can place billions of transistors operating at extremely high frequencies on a single chip as well as optical component. This offers a plethora of new opportunities that prior silicon chips could not address. In this talk, I will discuss a holistic design approach to integrated circuits leading to yet further proliferation of such technologies into our daily lives. We will discuss some of its exciting results, including low-cost tera-hertz imagers, nano-photonic coherent cameras capable of forming 3D images, optical phased arrays, space-based solar power transfer, self-healing circuits that repair themselves, and medical diagnostic and therapeutic devices solutions based on electromagnetic sensing and manipulation.

Bio
Professor Hajimiri’s group does research on electronics and photonics integrated circuits and their applications in various disciplines, including high-frequency and high-speed communications, sensing, imaging, and bio-sensing. His research group engages in both the theoretical analysis of the problems in integrated circuits as well as practical implementations of new systems.
Prof. Ali Hajimiri received his B.S. degree in Electronics Engineering from the Sharif University of Technology, and M.S. and Ph.D. degrees in electrical engineering from the Stanford University.

Before joining the Faculty of Caltech, he worked at Philips Semiconductors, where he worked on a BiCMOS chipset for GSM and cellular units, at Sun Microsystems working on the UltraSPARC microprocessor’s cache RAM design methodology, and with Lucent Technologies (Bell Labs), Murray Hill, NJ, where he investigated low-phase-noise integrated oscillators. In 1998, he joined the Faculty of the California Institute of Technology, Pasadena, where he is Bren Professor of Electrical Engineering and Medical Engineering, Director of Caltech Holistic Integrated Circuit Laboratory, and co-Director of the Space-based Solar Power Project. His research interests are high-speed and high-frequency electronics and photonics integrated circuits for applications in sensors, biomedical devices, photonics, and communication systems.

Prof. Hajimiri is the author of The Design of Low Noise Oscillators (Boston, MA: Springer) and has authored and coauthored close to 200 refereed journal and conference technical articles. He has been granted more than 90 U.S. patents and has many more pending applications. He has served on the Technical Program Committee of the International Solid-State Circuits Conference (ISSCC), as an Associate Editor of the IEEE Journal of Solid-State Circuits (JSSC), as an Associate Editor of IEEE Transactions on Circuits and Systems (TCAS): Part-II, a member of the Technical Program Committees of the International Conference on Computer Aided Design (ICCAD), Guest Editor of the IEEE Transactions on Microwave Theory and Techniques, and Guest Editorial Board of Transactions of Institute of Electronics, Information and Communication Engineers of Japan (IEICE).

He is a Fellow of National Academy of Inventors (NAI). Prof. Hajimiri was selected to the TR35 top innovator’s list. He is also a Fellow of IEEE and has served as a Distinguished Lecturer of the IEEE Solid-State and Microwave Societies. He is the recipient of Caltech’s Graduate Students Council Teaching and Mentoring award as well as the Associated Students of Caltech Undergraduate Excellence in Teaching Award. He was the Gold medal winner of the National Physics Competition and the Bronze Medal winner of the 21st International Physics Olympiad, Groningen, Netherlands. He was a co-recipient of the IEEE Journal of Solid-State Circuits Best Paper Award of 2004, the International Solid-State Circuits Conference (ISSCC) Jack Kilby Outstanding Paper Award, a co-recipient of RFIC best paper award, a two-time co-recipient of CICC best paper award, and a three-time winner of the IBM faculty partnership award as well as National Science Foundation CAREER award and Okawa Foundation award. In 2002, he co-founded Axiom Microdevices Inc., whose fully-integrated CMOS PA has shipped more than 250,000,000 units, and was acquired by Skyworks Inc. in 2009.

Registration Link:  http://sites.ieee.org/scv- sscs/upcoming-events/

The seminar is FREE and donation is accepted for refreshments (FREE SSCS members/$2 IEEE members/$5 non-members, pay online or at the door).
Eventbrite registration is required for everyone to attend the talk.

Date: May 17, 2018 (Thursday)
6:00-6:30pm
, Networking and refreshments
6:30-8:00pm, Technical Talk

Where: Texas Instruments Auditorium (Building E Visitor Center), 2900 Semiconductor Dr, Santa Clara, CA 95051, Directions and Map (to locate Building E)


“Circuits and Systems Design of Low Power Radios” by Dr. Imran Bashir

Date: May 19th, 2018

The IEEE Santa Clara Valley Circuits and Systems Chapter proudly sponsors the Technical Lecturer on 9:00 am – 10:30 am, Saturday, May 19, 2018 by Dr. Imran Bashir, titled:

“Circuits and Systems Design of Low Power Radios”

Abstract:                

This lecture will provide an overview of various emerging wireless standards for low power IoT applications. The main focus of the lecture will be circuits and systems design consideration for Bluetooth Low Energy (BLE) radios. A survey of emerging low power receivers based on coherent and sliding IF architectures will be presented. The lecture will include a deep dive into topics such as: two-point PLL modulation, power management, and circuit impairment study.

 

Bio:

Imran Bashir (S’99 – M’09 – SM’17) received the B.S.E.E. (summa cum laude) degree from the University of Texas at Arlington in 2001 and the M.S.E.E. and Ph.D degree from the University of Texas at Dallas in 2008 and 2014. He joined Texas Instruments in 2002 and was elected the prestigious title of Group Member of Technical Staff in 2006. He played a key role in the productization of GSM/EDGE SoCs based on the Digital RF Processor (DRP) technology. During the Fall of 2015, he was a Senior Research Fellow at the School of Electrical and Electronic Engineering at University College Dublin (UCD), Dublin, Ireland. He is currently working at Cypress Semiconductor Corp. and his research interests include digital PLLs, wideband modulators, polar transmitters, and low power wireless SoCs.

 

The technical lecture will be hosted on 2nd floor of Student Union at San Jose State University during the SJSU Annual poster event. COMPLIMENTARY breakfast and lunch is provided. FREE parking is available in the North Garage at SJSU campus. See details below.

 

Date: May 19, 2018 (Saturday)

8:30 am – 9:00 am Complimentary Breakfast
9:00 am – 10:30 am Lecture
10:30 am – 12:30 pm SJSU Event Poster Sessions
12:30 pm – 2:00 pm Complimentary Lunch

 

Locations:

Event: SJSU Student Union – 2nd Floor;

Address: 211 S 9th St, San Jose, CA 95112.

Parking: FREE parking at SJSU North Garage;

Address: b/w 9th and 10th St and E. San Fernando and Elizabeth St, Look for event organizers at parking gate with parking access code. For more information: http://www.sjsu.edu/parking/maps/garages/index.html

Admission Fee:
Free. Voluntary donations are always appreciated. Suggested donation: $2 for IEEE members, $5 for non-members.

IEEE Santa Clara Valley Circuits and Systems Chapter would like to thank the great support from San Jose State University.


IEEE Santa Clara Valley Section

Mission Statement

IEEE Santa Clara Valley Section inspires Silicon Valley professionals and students to stay connected and to collaborate by creating and providing leadership programs to educate and to stimulate technological innovation, and engineering excellence.

About IEEE SCV

The Santa Clara Valley (SCV) Section promotes the aims and objectives of the IEEE as stated in the IEEE Constitution and Bylaws. The Section concerns itself with all IEEE affairs taking place within the area prescribed by the IEEE as the territory of the SCV Section that geographically takes in all the peninsula cities south of Highway 92, plus the counties of Monterey, San Benito, Santa Clara, and Santa Cruz. The SCV, more popularly known as Silicon Valley, is the largest IEEE Section in the world in terms of membership as well as active chapters.

About IEEE

IEEE is the world’s largest professional association dedicated to advancing technological innovation and excellence for the benefit of humanity. IEEE and its members inspire a global community through IEEE’s highly cited publications, conferences, technology standards, and professional and educational activities. IEEE, pronounced “Eye-triple-E,” stands for the Institute of Electrical and Electronics Engineers.


Technology and Innovation- A talk by IEEE president-elect

Date: June 1st, 2018

The IEEE Circuits and Systems Society proudly co-sponsors this talk that is sponsored by the IEEE Silicon Valley section SAC.

Click here to register on eventbrite: Register Now

IEEE Life Fellow José M.F. Moura  has been chosen as 2018 IEEE president-elect. He will begin serving as IEEE president on 1 January 2019. IEEE SCV section members who care for member empowerment are instrumental in nominating Prof. Moura as a petition candidate and his eventual win as president-elect.  Please join us in listening to Prof. Moura!

Abstract

———–

Prof. Jose Moura will deliver two part talk. First part is more on technology, innovation and/or entrepreneurship -based on Prof Moura work. Second part is on his vision for IEEE: focus on membership and transparency at all IEEE levels and balance the operations budget of IEEE.

Agenda:

————

Have questions about Technology and Innovation- A talk by IEEE president-elect? Contact IEEE Silicon Valley Section SAC

Neuromorphic Chips: Addressing the Nanotransistor Challenge by Combining Analog Computation with Digital Communication by Dr. Kwabena Boahen

Date: June 27th, 2018

DESCRIPTION

PROGRAM

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:30 PM Talk
7:30 – 8:00 PM Q&A

Speaker:

Kwabena Boahen, Professor of Bioengineering and Electrical Engineering, Stanford University

Abstract:

As transistors shrink to nanoscale dimensions, trapped electrons–blocking “lanes” of electron traffic–are making it difficult for digital computers to work. In stark contrast, the brain works fine with single-lane nanoscale devices that are intermittently blocked (ion channels). Conjecturing that it achieves error-tolerance by combining analog dendritic computation with digital axonal communication, neuromorphic engineers (neuromorphs) began emulating dendrites with subthreshold analog circuits and axons with asynchronous digital circuits in the mid-1980s. Three decades in, they achieved a consequential scale with Neurogrid, the first neuromorphic system with billions of synaptic connections. Neuromorphs then tackled the challenge of mapping arbitrary computations onto neuromorphic chips in a manner robust to lanes intermittently–or even permanently–blocked by trapped electrons. Having demonstrated scalability and programmability, they now seek to encode continuous signals with spike trains in a manner that promises greater energy efficiency than all-analog or all-digital computing across a five-decade precision range.

About the Speaker:

Kwabena Boahen is a Professor of Bioengineering and Electrical Engineering at Stanford University, where he directs the Brains in Silicon Lab. He is a neuromorphic engineer who is using silicon integrated circuits to emulate the way neurons compute, and linking the seemingly disparate fields of electronics and computer science with neurobiology and medicine. His lab developed Neurogrid, a specialized hardware platform created at Stanford that enables the cortex’s inner workings to be simulated in real time–something outside the reach of even the fastest supercomputers. His interest in neural nets developed soon after he left his native Ghana to pursue undergraduate studies in Electrical and Computer Engineering at Johns Hopkins University, Baltimore, in 1985. He went on to earn a doctorate in Computation and Neural Systems at the California Institute of Technology in 1997. From 1997 to 2005 he was on the faculty of University of Pennsylvania, Philadelphia PA. With over ninety publications to his name, including a cover story in the May 2005 issue of Scientific American, his scholarship has been recognized by several distinguished honors, including the National Institute of Health Director’s Pioneer Award in 2006. In 2016, he was named a fellow of the Institute of Electrical and Electronic Engineers and of the American Institute for Medical and Biological Engineering. His 2007 TED talk, A Computer that Works like the Brain, has been viewed over half-a-million times.

Admission Fee:

Open to all to attend
(Online registration is needed. If you did not register, seating is not guaranteed.)

  • IEEE CIS members – free
  • Students – $3 (Register at Door $3)
  • IEEE (non-CIS) members – $7 (Register at Door $10)
  • Non-members – $10 (Register at Door $15)

You do not need to be an IEEE member to attend!

Eventbrite Link:

https://www.eventbrite.com/e/neuromorphic-chips-addressing-the-nanotransistor-challenge-by-combining-analog-computation-with-tickets-46793509647?aff=ebdssbdestsearch


Leveraging intelligent machines to assist Analog design exploration : ID-Xplore with Dr. Ramy Iskander

Date: June 28th, 2018

Event hosted by:

IEEE Santa Clara Valley Section

Eventbrite Registration Link

PROGRAM

6:30 – 7:00 PM Networking & Refreshments
7:00 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Abstract:

While design of digital systems needs few design iterations, due to strong maturity of design tools, analog systems need many design iterations. The analog design industry (ADI) acknowledges a strong business need to detect and eliminate the front-end analog design errors. Today’s commercially available design tools do not allow ADI actors easily to identify these errors up front and thus alleviate their additional design costs early on. This seemed to be an area where machine intelligence could help. The speaker has been exploring this possibility and has since developed a commercially available tool to address this area.

This talk will reveal the technology behind ID-XploreTM as the first attempt to create a true cognitive analog design system. ID-XploreTM is capable of detecting human design errors while designing circuits in the continuous analog world. ID-XploreTM can then suggest several resolution schemes to eliminate these errors seamlessly. The term cognitive refers to the fact that a new type of perceptron that incorporates analog domain knowledge was invented by Intento Design R&D team. This perceptron does not need deep learning since it incorporates domain knowledge instead of raw data. ID- XploreTM is not an expert system and does not have predefined templates for circuits, design rules, constraints, or layouts.

Intento team describes it as a cognitive and autonomous perceptron since it solves any given problem in the circuit in a very limited number of iterations. The difference between an expert system (all the rage a few decades ago) and Intento’s approach will be explained. Intento Design believes that the cognitive computing era is strongly rising beyond AI. “It is not about replacing HUMAN in daily tasks. It is about boosting human skills through COLLABORATION and ASSISTED BRAINSTORMING between HUMAN and INTELLIGENT MACHINES.” says Dr. Iskander.

Bio:

Dr. Ramy Iskander serves as the CEO and President of Intento Design which he founded in 2015. Intento Design has a team of 18 members consisting of 11 PhDs in EDA, CAD, AMS Circuit design, Semiconductor physics, Mathematics, Software engineering and talented Senior Developers.

Intento Design, is currently bringing to the EDA market two disruptive and innovative products:

  • ID-XploreTMfor fast analog IP design and migration
  • ID-SubstrateTM for prediction and prevention of substrate noise coupling effects including minority carriers propagation.

 

Dr.  Iskander received the M.Sc. degree in 2004 and the Ph.D. degree in 2008, from the Laboratoire d’Informatique de Paris 6 (LIP6) at Universit´e Pierre et Marie Curie (UPMC), Paris, France. Since 2008, Dr. ISKANDER is also  an Associate Professor within the Laboratoire LIP6 at UPMC. Prior to this , he worked for more than 10 years in international EDA companies. He published more than 100+ papers on analog design automation methods for nanometer technologies covering modeling, simulation, synthesis, layout generation and technology migration. He has served as a reviewer for French National ANR projects and for several book reviews, international conferences and international journal papers. He currently serves as  the scientific coordinator of the European FP7/ICT/Green Car project called AUTOMICS covering modeling and simulation of substrate coupling effects for automotive applications.

Venue:

QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA 95051

Admission Fee:

Open to all to attend
Online registration is recommended to guarantee seating.

You do not need to be an IEEE member to attend!

 


Review of LiDAR, Localization and Object Processing for Safe Autonomous Systems by Dr. Gunnam

Date: July 19th, 2018

“Review of LiDAR, Localization and Object Processing for Safe Autonomous Systems”, Dr. Kiran Gunnam, Distinguished Engineer, Western Digital

TIME: 6:00PM – 8:00PM

Add to Calendar

LOCATION: Texas Instruments Silicon Valley Auditorium, 2900 Semiconductor Dr. , Building “E”, Santa Clara, CA, View Map

DESCRIPTION

IEEE Silicon Valley Solid-State Circuits Society (SSCS)

Cosponsored by IEEE Silicon Valley Circuits and Systems Society (CASS)

Abstract:

Autonomous systems need to use a wide range of sensing technologies such as LiDAR, camera and RADAR to provide a robust sensing and perception of the environment. First part of this talk reviews the state-of-the art architectures for LiDARs that goes in detail about lasers, photo diodes, architecture for transmitters and receivers including time to digital conversion, matched filtering for detection and cross-talk avoidance. Second part of the talk reviews the recent groundbreaking work (by Apollo AI) in integrated perception that can be easily embedded into the LiDAR sensors which consists of LiDAR+camera+IMU fusion, robust mapping, localization and object processing for safe autonomous systems.

Bio:

Dr. Kiran Gunnam is an innovative technology leader with vision and passion who effectively connects with individuals and groups. Dr. Gunnam’s breakthrough contributions are in the areas of advanced error correction systems, storage class memory systems and vision based navigation systems. He has helped drive organizations to become industry leaders through ground-breaking technologies. Dr. Gunnam has 70 issued patents and 100+ patent applications/invention disclosures on algorithms, computing and storage systems. He is the lead inventor/sole inventor for 90% of them. Dr. Gunnam’s patented work has been already incorporated in more than 2 billion data storage and WiFi chips and is set to continue to be incorporated in more than 500 million chips per year. Dr. Gunnam served as IEEE Distinguished Speaker and Plenary Speaker for 20+ events and international conferences and more than 2000 attendees in USA, Canada and Asia benefited from his lecture talks. He also teaches graduate level course focused on machine learning systems at Santa Clara University.

The seminar is FREE and donation is accepted for refreshments (FREE SSCS/CAS members/$2 IEEE members/$5 non-members)

Eventbrite registration is required for everyone to attend the talk.

Venue:

Texas Instruments Silicon Valley Auditorium 2900 Semiconductor Dr., Building E, Santa Clara, CA 95051 Directionsand Map (to locate Building E). 

Time: July 19 (Thursday) evening 6:00PM-8:00PM

Networking and Refreshments: 6:00 PM – 6:30 PM 

Technical Talk: 6:30 PM – 8:00 PM


Distinguished Lecturer Seminar by Prof. Gabor C. Temes: “A 13b ENOB Noise-Shaping SAR ADC with a Two-Capacitor DAC”

Date: July 26th, 2018

DESCRIPTION

“A 13b ENOB Noise-Shaping SAR ADC with a Two-Capacitor DAC”

Prof. Gabor C. Temes, School of EECS, Oregon State University

IEEE Santa Clara Valley Section

Eventbrite Registration Link

PROGRAM

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Watch the lecture live on Zoom from your home and anywhere around the world! Register now and you will be sent details one day before the event.

Abstract:

An active noise-shaping successive-approximation-register (SAR) analog-to-digital converter is described. Instead of binary-weighted capacitors, it uses two equal-valued capacitors as the embedded digital-to-analog converter (DAC). Thus, the capacitance spread in the DAC is much smaller than that of the conventional binary-weighted capacitor array, and the mismatcherror can be greatly reduced. The circuit provides first-order noise shaping, which can improve the ADC’s linearity even for a small oversampling ratio. Also, the proposed architecture uses a monotonic approximation procedure, which requires fewer conversion steps than for a conventional SAR ADCs. The ADC was fabricated in 0.18 um CMOS technology. For a 2 kHz signal bandwidth, it achieved a 78.8 dB SNDR. It consumes 74.2 mW power from a 1.5 V power supply. The performance can be drastically improved by introducing noise mitigation schemes and higher-order noise shaping.

Bio:

Gabor C. Temes received the Ph.D. degree in Electrical Engineering from the University of Ottawa, ON, Canada, in 1961, and an honorary doctorate from the Technical University of Budapest, Budapest, Hungary, in 1991.

He held academic positions at the Technical University of Budapest, Stanford University and the University of California at Los Angeles. He worked in industry at Northern Electric R&D Laboratories and at Ampex Corp. He is now a Professor in the School of Electrical Engineering and Computer Science at Oregon State University.

Dr. Temes received the IEEE Graduate Teaching Award in 1998, and the IEEE Millennium Medal in 2000. He was the 2006 recipient of the IEEE Gustav Robert Kirchhoff Award, and the 2009 IEEE CAS Mac Valkenburg Award. He received the 2017 Semiconductor Industry Association-SRC University Researcher Award. He is a member of the National Academy of Engineering.

Venue:

Cypress Semiconductor Corporation, Main Auditorium in Building 6, 198 Champion Ct, San Jose, CA 95134

Convenient VTA light rail access from Mountain View and downtown San Jose.

Live Broadcast:

Lecture will be broadcast live on Zoom. Registrants will be sent the conference details one day before the event.

Admission Fee:

Open to all to attend
Online registration is recommended to guarantee seating.

You do not need to be an IEEE member to attend!

 


Lecture by Dr. Mihai Banu: “Massive MIMO Active Antenna Arrays for Advanced Wireless Communications”

Date: August 9th, 2018

DESCRIPTION

“Massive MIMO Active Antenna Arrays for Advanced Wireless Communications”

Dr. Mihai Banu, CTO, Blue Danube Systems, Santa Clara CA

IEEE Santa Clara Valley Section

Eventbrite Registration Link

PROGRAM

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Watch the lecture live on Zoom from your home and anywhere around the world! Register now and you will be sent details one day before the event.

Abstract:

Recently, many experts in academia and industry have been strongly advocating the concept of Massive MIMO for application in 4G and 5G systems. While the push for larger base station antenna aperture is probably the right idea for many systems, there are important subtleties in the Massive MIMO concept, which make its practical application far from straightforward. These include HW complexity, channel estimation challenges, signal coherency issues, radio chain to antenna mapping, and multi-band designs. This talk will discuss the main types of Massive MIMO systems pointing out their benefits and limitations for various RAN systems and frequency bands. This talk will also present field trial results for Blue Danube Massive MIMO products operating in mid-band spectrum.

Bio:

Dr. Banu has over 30 years experience in circuits and systems R&D, with emphasis on analog, radio frequency and mixed-signal integrated circuits.

His experience encompasses many areas from invention and demonstration of new circuits and system concepts, to design methodologies and product development.

Dr. Banu is Founder of Blue Danube Systems, which received Series A venture capital funding and started operations in 2013. He developed the Blue Danube Systems technology concepts at MHI Consulting, a small consulting firm founded and owned by Dr. Banu since 2006. Prior to that, he was R&D director at Agere Systems, working on analog circuits, RF systems for wireless LANs and wireless circuits research.

From 1995 to 2000, Dr. Banu was Head of the Communications Circuits Research department at Lucent Technologies, where he was responsible for advanced work in circuit design and Si technology process-device enhancements including SiGe BiCMOS. From 1980 to 1995, he was a Member of Technical Staff at AT&T Bell Laboratories in the Communications Sciences Division, the Physical Sciences Division and the VLSI Research Department.

Dr. Banu is author of more than 30 technical papers, several book chapters and many U.S. and international patents. As a recognized IC design expert, he was invited to contribute in many panels and workshops at major international conferences, as well as teach short courses.

He received his bachelor’s, master’s, and Ph.D. degrees in electrical engineering from Columbia University and he is an IEEE Fellow.

Venue:

Cypress Semiconductor Corporation, Main Auditorium in Building 6, 198 Champion Ct, San Jose, CA 95134

Convenient VTA light rail access from Mountain View and downtown San Jose.

Live Broadcast:

Lecture will be broadcast live on Zoom. Registrants will be sent the conference details one day before the event.

Admission Fee:

Open to all to attend
Online registration is recommended to guarantee seating.

You do not need to be an IEEE member to attend!


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