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Date: September 25th, 2019
Educational Seminar: Control for Power Electronics (Co-sponsored Event)

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2019 Events


“Mixed-Signal Processing For Machine Learning”, Dr. Daniel Bankman, Stanford University

Date: January 31st, 2019

Time: 6:00-8:00PM

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Drive, Santa Clara, CA 95051

Directions: TI-BldgE-Auditorium.pdf

Registration Link: (Mandatory) : Link

Registration Fee: FREE, Donation Requested

IEEE SSCS/CAS/SPS/CS members: FREE
IEEE members – $2 donation
Non-members – $5

Abstract:

Recent advancements in machine learning algorithms, hardware, and datasets have led to the successful deployment of deep neural networks (DNNs) in various cloud-based services. Today, new applications are emerging where sensor bandwidth is higher than network bandwidth, and where network latency is not tolerable. By pushing DNN processing closer to the sensor, we can avoid throwing data away and improve the user experience. In the long term, it is foreseeable that such DNN processors will run on harvested energy, eliminating the cost and overhead of wired power connections and battery replacement. A significant challenge arises from the fact that DNNs are both memory and compute intensive, requiring millions of parameters and billions of arithmetic operations to perform a single inference. In this talk, I will present circuit and architecture techniques that leverage the noise tolerance and parallel structure of DNNs to bring inference systems closer to the energy-efficiency limits of CMOS technology.

In the low SNR regime where DNNs operate, thermally-limited analog signal processing circuits are more energy-efficient than digital. However, the massive scale of DNNs favors circuits compatible with dense digital memory. Mixed-signal processing allows us to integrate analog efficiency with digital scalability, but close attention must be paid to energy consumed at the analog-digital interface and in memory access. Binarized neural networks minimize this overhead, and hence operate closer to the analog energy limit. I will present a mixed-signal binary convolutional neural network processor implemented in 28 nm CMOS, featuring a weight-stationary, parallel-processing architecture that amortizes memory access across many computations, and a switched-capacitor neuron array that consumes an order of magnitude lower energy than synthesized digital arithmetic at the same application-level accuracy. I will provide an apples-to-apples comparison of the mixed-signal, hand-designed digital, and synthesized digital implementations of this architecture. I will conclude with future research directions centered around the idea of training neural networks where the transfer function of a neuron models the behavior of an energy-efficient, physically realizable circuit.

Bio:

Daniel Bankman is a PhD candidate in the Department of Electrical Engineering at Stanford University, advised by Prof. Boris Murmann. His research focuses on mixed-signal processing circuits, hardware architectures, and neural architectures capable of bringing machine learning closer to the energy limits of scaled semiconductor technology. During his PhD, he demonstrated that switched-capacitor circuits can significantly lower the energy consumption of binarized neural networks while preserving the same application-level accuracy as digital static CMOS arithmetic. Daniel received the S.B. degree in electrical engineering from MIT in 2012 and the M.S. degree from Stanford in 2015. He has held internship positions at Analog Devices Lyric Labs and Intel AI Research, and served as the instructor for EE315 Analog-Digital Interface Circuits at Stanford in 2018.


Lecture by Dr. Ratnesh Kumar “Vehicle Re-identification for Smart Cities: A New Baseline Using Triplet Embedding”

Date: January 31st, 2019

DESCRIPTION:

“Vehicle Re-identification for Smart Cities: A New Baseline Using Triplet Embedding”

Dr. Ratnesh Kumar, Deep Learning Architect, Nvidia Corporation, San Jose, CA

Event Organized By:

Circuits and Systems Society (CASS) of the IEEE Santa Clara Valley Section

Co-sponsors:

Registration Link:

Click here to register.

PROGRAM:

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Watch the lecture live on Zoom from your home and anywhere around the world! Register now and you will be sent details one day before the event.

Abstract:

With the proliferation of surveillance cameras enabling smart and safer cities, there is an ever-increasing need to re-identify vehicles across cameras. Typical challenges arising in smart city scenarios include variations of viewpoints, illumination and self occlusions. In this talk we will discuss an exhaustive evaluation of deep embedding losses applied to vehicle re-identification, and demonstrate that using the best practices for learning-embeddings outperform most of the previous approaches in vehicle re-identification.

Bio:

Ratnesh Kumar is currently a Deep Learning Architect at Nvidia USA from January 2017. He has obtained his PhD from STARS team at Inria, France in Dec 2014. His research focus during PhD was on long term video segmentation using optical flow and multiple object tracking. Subsequently he worked as Postdoc at Mitsubishi Electric Research Labs (MERL) Cambridge, Boston, on detection actions in streaming videos. He also holds Bachelors in Engineering from Manipal University, India and Master of Science from University of Florida at Gainesville, USA. At Nvidia since 2017, his focus is on leveraging deep learning on hardware accelerated GPU platforms to solve several problems in video analytics ranging from object detection to re-identification and action detection, with low latency and high data throughput. He is co-author of 9 scientific publications in conferences and journals and has several patents pending. He is also a plenary speaker at IEEE International Conference on Image Processing Applications and Systems (IPAS) 2018. He has also served as organizing member for AI-CITIES 2018 challenge for smart cities.

Venue:

Cypress Semiconductor Corporation, Main Auditorium in Building 6, 198 Champion Ct, San Jose, CA 95134

Convenient VTA light rail access from Mountain View and downtown San Jose.

Live Broadcast:

Lecture will be broadcast live on Zoom. Registrants will be sent the conference details one day before the event.

Admission Fee:

Non-IEEE: $5

Students (non-IEEE): $3

IEEE Members (not members of CASS or SSCS): $3

IEEE CASS and SSCS Members: Free

Open to all to attend.

Online registration is recommended to guarantee seating.


“Cryogenic CMOS Interfaces for Large-Scale Quantum Computers” Prof. Fabio Sebastiano Delft University of Technology, Delft, The Netherlands

Date: February 21st, 2019

Cryogenic CMOS Interfaces for Large-Scale Quantum Computers

Prof. Fabio Sebastiano
Delft University of Technology, Delft, The Netherlands

6:00-6:30pm, Networking and refreshments
6:30-8:00pm, Technical Talk

Abstract:

Quantum computers hold the promise to ignite the next technological revolution as the classical computer did for last century’s digital revolution, by efficiently solving problems that are intractable by today’s computers. By enabling the efficient simulation of quantum systems, quantum computing will allow both the optimization of existing industrial processes and the synthesis of new drugs and materials, thus representing an unprecedented game changer with the potential to disrupt entire industries, create new ones and radically change our lives.

Quantum computers rely on processing the information stored in quantum bits (qubits) that must be typically cooled well below 1 K for proper operation. Performing operations on qubits requires a classical (i.e. non-quantum) electronic interface, which is currently implemented at room temperature for the few qubits available today. However, future quantum processors will comprise thousands or even millions of qubits. To avoid the unpractical requirement of thousands of cables from the cryogenic refrigerator to the room-temperature electronics, the electronic interface must operate at cryogenic temperatures as close as possible to the qubits.

This talk will address the challenges of building such a scalable cryogenic electronic interface, focusing on the use of standard CMOS technology. A brief introduction to quantum computers and their operation will be given, followed by a description of their hardware implementation and their requirements in terms of electronic control and read-out. To enable the reliable design of cryogenic circuits, two main ingredients are required: on one hand, compact models for the cryogenic CMOS devices and, on the other hand, a comprehensive methodology to co-design the electronics and the quantum processor. After addressing those aspects, we will demonstrate the design and the functionality of complex analog and digital systems operating at 4 K, thus showing that cryogenic CMOS is a viable technology to enable large-scale quantum computing

Bio:

Fabio Sebastiano holds degrees from University of Pisa, Italy (B.Sc., 2003, cum laude; M.Sc., 2005, cum laude), from Sant’Anna School of Advanced Studies, Pisa, Italy (M.Sc., 2006, cum laude) and from Delft University of Technology, The Netherlands (Ph.D., 2011).

From 2006 to 2013, he was with NXP Semiconductors Research in Eindhoven, The Netherlands, where he conducted research on fully integrated CMOS frequency references, nanometer-CMOS temperature sensors and area-efficient interfaces for magnetic sensors. In 2013, he joined Delft University of Technology, where he is currently an Assistant Professor. His main research interests are cryogenic electronic interfaces, quantum computation, fully-integrated frequency references and electronic interfaces for smart sensors.

Dr. Sebastiano holds 10 patents, and has co-authored 1 book and over 60 technical publications. He has given invited talks and courses at several international conferences including the International Solid-State Circuits Conference (ISSCC). He was co-recipient of the 2008 ISCAS Best Student Paper Award and of the 2017 DATE best IP award. Fabio is a senior member of IEEE and a Distinguished Lecturer of the IEEE Solid-State Circuit Society.

Seminar Info:  http://sites.ieee.org/scv-sscs/upcoming-events/

The seminar is FREE and donation is accepted for refreshments (FREE SSCS members/$2 IEEE members/$5 non-members, pay online or at the door).
Eventbrite registration is required for everyone to attend the talk: https://www.eventbrite.com/e/cryogenic-cmos-interfaces-for-large-scale-quantum-computers-prof-fabio-sebastiano-delft-university-tickets-56845662908

Where: Texas Instruments Auditorium (Building E Visitor Center), 2900 Semiconductor Dr, Santa Clara, CA 95051, Directions and Map (to locate Building E)


“Reflections On High-Performance Fractional-N Frequency Synthesis”, by Prof. Peter Kennedy FIEEE & “Sub-Sampling Techniques for mm-Wave and Digital Phase-Locked Loops”, by Prof. Teerachot Siriburanon, University College Dublin, Ireland

Date: February 22nd, 2019

Two Lectures On PLLs:

“Sub-Sampling Techniques For Mm-Wave And Digital Phase-Locked Loops”

Prof. Teerachot Siriburanon, University College Dublin, Dublin, Ireland

“Reflections On High-Performance Fractional-N Frequency Synthesis”

Prof. Peter Kennedy FIEEE, University College Dublin, Ireland

Event Organized By:

Circuits and Systems Society (CASS) of the IEEE Santa Clara Valley Section

Co-sponsors:

PROGRAM:

4:30 – 5:00 PM Networking & Refreshments
5:00 – 6:00 PM Lecture 1: “Sub-Sampling Techniques for mm-Wave and Digital Phase-Locked Loops” by Prof. Siriburanon

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Lecture 2: “Reflections on High-Performance Fractional-N Frequency Synthesis” by Prof. Kennedy
7:45 – 8:00 PM Q&A/Adjourn

Zoom broadcast may not be possible. In person attendance requested.

REGISTRATION:

Lecture 1:

Abstract:

This talks presents the development of low-power and low-phase-noise phase-locked loops (PLLs) using sub-sampling techniques. The method in which gains significant interests in the past decade to apply in low-jitter PLLs. In the first part of the talk, the consideration of architectures for mm-wave frequency generation will be reviewed and the method using sub-sampling phase detection in sub-harmonic injection locked architecture for 60GHz frequency synthesis will be discussed. The design of key building blocks will be presented in order to achieve low power consumption with good performance, e.g. injection-locked frequency divider and mm-wave oscillators. In the second part of the talk, sub-sampling technique is extended for the use in all-digital phase-locked loop in digital sub-sampling architecture. Finally, the methods to extend sub-sampling techniques in fractional-N operation and recent developments in the field will be discussed.

Bio:

Teerachot Siriburanon received the B.E. degree in Telecommunications Engineering from Sirindhorn International Institute of Technology (SIIT), Thammasat University, Pathumthani, Thailand, in 2010, the M.E. degree and Ph.D. degree in Physical Electronics from Tokyo Institute of Technology, Tokyo, Japan, in 2012 and 2016, respectively. In 2016, he joined University College Dublin (UCD), Dublin, Ireland, as a postdoctoral researcher and later received Marie Skłodowska-Curie Individual Fellowship in 2017. Since 2019, he has been an Assistant Professor with University College Dublin (UCD), Dublin, Ireland.

Dr. Siriburanon was the recipient of the Japanese Government (MEXT) Scholarship, the Young Researcher Best Presentation Award at Thailand-Japan Microwave in 2013, the ASP-DAC Best Design Award in 2014 and 2015, the IEEE SSCS Student Travel Grant Award in 2014, the IEEE SSCS Predoctoral Achievement Award in 2016, and the Tejima Research Award in 2016.

Lecture 2:

Abstract:

Fractional-N frequency synthesizers are widely used in electronic systems to generate carrier or clock frequencies that are not simple integer multiples of a reference frequency. As synthesizer architectures are pushed to the limits of their performance, new insights have been gained into underlying mechanisms for excess noise and spur generation. With these insights come strategies for addressing underlying causes. This lecture presents an overview of fractional-N frequency synthesis, highlighting fundamental architecture-related issues which can degrade performance, insights into the root causes of the problems, and some ideas which help to ameliorate the situation.

Bio:

Michael Peter Kennedy is Professor of Microelectronic Engineering at University College Dublin and President of the Royal Irish Academy (RIA). He received his PhD from the University of California at Berkeley in 1991 and the DEng from the National University of Ireland in 2010. He has published over 390 technical articles, including monographs and patents, covering “blues skies” to applied research, from chaos theory to circuit design. He received the IEEE Millenium and Golden Jubilee Medals, and the inaugural RIA Parsons Award in Engineering Sciences. He was made a Fellow of the IEEE in 1998 for contributions to the theory of neural networks and nonlinear dynamics and for leadership in nonlinear circuits research and education. From 2005 to 2007, he was President of the European Circuits Society and Vice-President of the IEEE Circuits and Systems (CAS) Society. He was a Distinguished Lecturer of the IEEE during 2012‒13. He is founding Director of the Microelectronics Industry Design Association and Microelectronic Circuits Centre Ireland. He has commercialized efficient test algorithms for data converters, behavioral simulation strategies for PLLs, and architectures for high-performance frequency synthesizers.

Venue:

Texas Instruments, Building E Conference Center, 2900 Semiconductor Blvd., Santa Clara, CA 95051

Live Broadcast:

Live broadcast may not be available. In person attendance requested.

Admission Fee:

All admissions free. Suggested donations to cover food and water:

Non-IEEE: $5, Students (non-IEEE): $3, IEEE Members (not members of CASS or SSCS): $3

Online registration is recommended to guarantee seating.


CASS Distinguished Lecturer Event “Energizing and Powering Micro-systems” by Dr. Gabriel A. Rincón-Mora, Georgia Tech

Date: February 28th, 2019

DESCRIPTION:

“Energizing and Powering Microsystems”

Dr. Gabriel A. Rincón-Mora, Georgia Tech

Event Organized By:

Circuits and Systems Society (CASS) of the IEEE Santa Clara Valley Section

Co-sponsors:

PROGRAM:

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Zoom broadcast may not be possible. Lecture will not be recorded. In person attendance requested.

Registration:

Click here to register.

Abstract:

Networked wireless microsensors can not only monitor and manage power consumption in small- and large-scale applications for space, military, medical, agricultural, and consumer markets but also add cost-, energy-, and life-saving intelligence to large infrastructures and tiny devices in remote and difficult-to-reach places. Ultra-small systems, however, cannot store sufficient energy to sustain monitoring, interface, processing, and telemetry functions for long. And replacing or recharging the batteries of hundreds of networked nodes can be labor intensive, expensive, and oftentimes impossible. This is why alternate sources are the subject of ardent research today. Except power densities are low, and in many cases, intermittent, so supplying functional blocks is challenging. Plus, tiny lithium-ion batteries and super capacitors, while power dense, cannot sustain life for extended periods. This talk illustrates how emerging microelectronic systems can draw energy from elusive ambient sources to power tiny wireless sensors.

Bio:

Gabriel A. Rincón-Mora has been a Professor at the Georgia Institute of Technology (Georgia Tech) since 2001 and Visiting Professor at National Cheng Kung University in Taiwan since 2011 and was Adjunct Professor at Georgia Tech in 1999-2001 and Design Team Leader at Texas Instruments in 1994-2003. He is a Fellow of the National Academy of Inventors, a Fellow of the IEEE, and a Fellow of the Institution of Engineering and Technology. He was inducted into Georgia Tech’s Council of Outstanding Young Engineering Alumni and named one of “The 100 Most Influential Hispanics” by Hispanic Business magazine. He received the National Hispanic in Technology Award from the Society of Hispanic Professional Engineers (SHPE), Charles E. Perry Visionary Award from Florida International University (FIU), Three-Year Patent Award from Texas Instruments, Orgullo Hispano Award from Robins Air Force Base, Hispanic Heritage Award from Robins Air Force Base, and Commendation Certificate from former Lieutenant Governor Cruz M. Bustamante of California. His scholarly products include 9 books, 4 book chapters, 42 patents, over 170 articles, over 26 commercial power-chip products, and over 130 international speaking engagements.

Venue:

Texas Instruments, Building E Conference Center, 2900 Semiconductor Blvd., Santa Clara, CA 95051

Live Broadcast:

Live broadcast may not be available. No recording.

Admission Fee:

All admissions free. Suggested donations to cover food and water:

Non-IEEE: $5, Students (non-IEEE): $3, IEEE Members (not members of CASS or SSCS): $3

Online registration is recommended to guarantee seating.


ValleyML.ai Event: State of AI and ML-Spring 2019

Date: April 4th, 2019

Description

Please visit this event page for more details.

In this event as part of series of regularly planned events, we plan to cover the state-of-the art advances in AI technology. For this event, we focus on AI Accelerators, Self-Driving and Face Processing. We feature five thought leaders from Computing, Autonomous systems and Computer Vision.

Each talk is 45 minutes followed by 10 minutes for Q&A.

Check In: 1.00pm-1.30pm

Key Note : “Emergence of RISC-V computer architecture: embedded applications and machine learning acceleration”, Dr. Zvonimir Bandić, Sr. Director of Next Generation Platform Technologies at Western Digital Corporation, Board of Directors member of RISC-V foundation. 1.30pm-2.25pm

Talk 2:“Accelerating Deep Neural Network Inference with FPGAs”, Mr. Rahul Nimaiyar, Director, Data Center IP Solutions at Xilinx. 2.30pm-3.25pm

Talk 3 “An ASIC approach to unlock deep learning innovation”, Dr. Carlos Macian, Sr. Director AI Strategy and Products at eSilicon. 3.30pm-4.25pm

Break for Networking and Snacks: 4.25pm-5.00pm

Talk 4: “Expectations from an AI Co-Processor for ADAS and Autonomous Driving”, Dr. Vikram Narayan, Head of AI & Computer Vision, the ADAS Group of Visteon Corporation, 5.00pm-5.55pm

Talk 5: “Introduction to Face Processing with Computer Vision”, Mr.Gabriel Bianconi, Founder, Scalar Research, 6:00pm-6.55pm

Program Chair: Dr. Kiran Gunnam, Distinguished Engineer – Machine Learning & Computer Vision

Please visit this event page for more details.

See this direct link for program schedule, speaker bios and abstracts.


“eFPGA technology – for Compute, Network and Storage Acceleration”, Volkan Oktem

Date: April 10th, 2019

Event organized by Chip Chat, co-sponsored by Circuits and Systems Society.

TOPIC:
“eFPGA technology – for Compute, Network and Storage Acceleration”
The speaker , Volkan Oktem, Senior Director of Product Applications at Achronix Semiconductor will discuss the eFPGA technology and how Achronix Speedcore Customizable eFPGA Technology achieves this acceleration for the modern day workloads.

SPEAKERS BIO:

Volkan Oktem is the Senior Director of Product Applications at Achronix Semiconductor. Volkan has 13 years’ of experience in the semiconductor and FPGA industry. Prior to joining Achronix, Volkan worked in various production test and applications engineering roles at Altera Corporation, driving quality and customer solutions on 65nm, 40nm and 28nm high-end Stratix FPGAs. After joining Achronix in 2012, Volkan has built the applications organization to provide world class pre- and post-sales technical support, to generate collateral for standalone and embedded FPGA products, and to support engineering with bring-up and product planning. Volkan holds a B.S. from Lafayette College and a M.S. from Georgia Institute of Technology, both in Electrical and Computer Engineering.

AGENDA :
6:30pm – 7:00pm – Registration and Networking
7:00pm – 8:00pm – Talks
8:00pm – 8:30pm – Networking

LOCATION:

Synopsys Building B

690 E Middlefield Rd, Mountain View, CA 94043

REGISTRATION:

https://www.meetup.com/Chip-Chat/events/260208231/

NOTES :

1. Admission is free.

Suggested donation is $5/- to cover the expenses at Registration.
– Cash
– Venmo to chatchip6@gmail.com
– Onsite Credit Card payment

2. Confidential Information will not be discussed. Audience is requested
to refrain from asking questions related to confidential information.


“Enabling Wireless Autonomous Systems Using 5G” by Dr. Nageen Himayat, Intel Corporation

Date: April 11th, 2019

“Enabling Wireless Autonomous Systems Using 5G”

Dr. Nageen Himayat, Intelligent Distributed Edge Networks Labs, Intel Corporation

Registration Link:

Here.

Event Organized By:

Circuits and Systems Society (CASS) of the IEEE Santa Clara Valley Section

Co-sponsors:

PROGRAM:

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Zoom broadcast is TBD. In person attendance requested.

Abstract:

Enabling next generation of wireless autonomous systems (WAS), such as self-driving vehicles, industrial robots, drones, etc., promises huge economic as well as societal impact, but poses significant challenges in meeting the reliability, latency and scalability requirements of these safety critical applications. This talk will discuss some of these challenges, and highlight technologies that advance 5G/5G+ wireless networks, as well as co-design autonomous systems and wireless networks, towards addressing the stringent WAS requirements.

Bio:

Nageen Himayat is a Principal Engineer, and Director of Intelligent Distributed Edge Networks Labs, at Intel, where she conducts research on distributed learning and data centric protocols over 5G/5G+wireless networks. Her research contributions span areas such as machine learning for wireless, millimeter wave and multi-radio heterogeneous networks, cross layer radio resource management, and non-linear signal processing techniques.

Prior to Intel, Dr. Himayat was with Lucent Technologies and General Instrument Corp, where she developed standards and systems for both wireless and wire-line broadband access networks. Dr. Himayat obtained her B.S.E.E degree from Rice University, and her Ph.D. degree from the University of Pennsylvania. She also holds an MBA degree from the Haas School of Business at University of California, Berkeley.

Venue:

QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA 95051

Live Broadcast:

TBD.

Admission Fee:

All admissions free. Suggested donations to cover food and water:

Non-IEEE: $5, Students (non-IEEE): $3, IEEE Members (not members of CASS or SSCS): $3

Online registration is recommended to guarantee seating.


CASS Distinguished Lecturer Event “Flexible Radios And Flexible Networks” Dr. Alyssa Apsel

Date: April 25th, 2019

CASS Distinguished Lecturer Event

“Flexible Radios And Flexible Networks”

Dr. Alyssa Apsel, Cornell University

Event Organized By:

Circuits and Systems Society (CASS) of the IEEE Santa Clara Valley Section

Co-sponsors:

REGISTRATION:

Here.

PROGRAM:

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Zoom broadcast is TBD. In person attendance requested.

Abstract:

Over the past decades the world has become increasingly connected, with communications driving both markets and social movements. Low power electronics, efficient communications, and better battery technology have all contributed to this revolution, but the cost and power required for these systems must be pushed further to make cheap, ubiquitous, seamless communication accessible to a wider community. In this talk I will discuss two engineering approaches to this problem. I will look at various approaches to drive the power down in radio networks that span across circuits and systems. I will also look at creative biologically inspired approaches to enabling very low power networks and IoT. Finally, I will discuss how by adding flexibility and building reconfigurable hardware, we can likewise build lower power and less costly consumer systems that can adapt across protocols and networks and work under changing device technologies.

Bio:

Alyssa Apsel received the B.S. from Swarthmore College in 1995 and the Ph.D. from Johns Hopkins University, Baltimore, MD, in 2002. She joined Cornell University in 2002, where she is currently Director of Electrical and Computer Engineering. She was a Visiting Professor at Imperial College, London from 2016-2018. The focus of her research is on power-aware mixed signal circuits and design for highly scaled CMOS and modern electronic systems. Her current research is on the leading edge of ultra-low power and flexible RF interfaces for IoT. She has authored or coauthored over 100 refereed publications including one book in related fields of RF mixed signal circuit design, ultra-low power radio, interconnect design and planning, photonic integration, and process invariant circuit design techniques resulting in ten patents. She received best paper awards at ASYNC 2006 and IEEE SiRF 2012, had a MICRO “Top Picks” paper in 2006, received a college teaching award in 2007, received the National Science Foundation CAREER Award in 2004, and was selected by Technology Review Magazine as one of the Top Young Innovators in 2004. She is a Distinguished Lecturer of IEEE CAS for 2018-2019, and has also served on the Board of Governors of IEEE CAS (2014-2016) and as an Associate Editor of various journals including IEEE Transactions on Circuits and Systems I and II, and Transactions on VLSI. She has also served as the chair of the Analog and Signal Processing Technical committee of ISCAS 2011, is on the Senior Editorial Board of JETCAS, as Deputy Editor in Chief of Circuits and Systems Magazine, and as the co-founder and Chair of ISCAS Late Breaking News. In 2016, Dr. Apsel co-founded AlphaWave IP Corporation, a multi-national Silicon IP provider focused on multi-standard analog Silicon IP solutions for the world of IOT.

Venue:

QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA 95051

Live Broadcast:

TBD.

Admission Fee:

All admissions free. Suggested donations to cover food and water:

Non-IEEE: $5, Students (non-IEEE): $3, IEEE Members (not members of CASS or SSCS): $3

Online registration is recommended to guarantee seating.


Intelligent Ear-Level Devices for Hearing Enhancement and Health and Wellness Monitoring

Date: May 9th, 2019

IEEE SPS Distinguished Industry Speaker Talk:

Intelligent Ear-Level Devices for Hearing Enhancement and Health and Wellness Monitoring

Event Sponsored and Organized By:

IEEE SPS Chapter of Santa Clara Valley

Co-sponsor:

IEEE EMBS Chapter of San Francisco

Solid-State Circuits Society(SSCS)

Circuits and Systems Society – Santa Clara Valley Chapter (CASS-SCV)

Registration Link: here.

DIS Speaker:

Tao Zhang, Ph.D., Director of Signal Processing Research Department, Starkey Hearing Technologies

(6600 Washington Ave. S., Eden Prairie, MN 55344, USA)

Location: AMD 2485 Augustine Dr, Santa Clara, CA 95054 (Google Maps)

Venue Details: Please park in parking structure close to the building on Octavius Drive. First building after passing AMD and the road does a curve to the right. Please walk around AMD building to the Highway 101 side to the visitor entrance.

Schedule:

6:30pm-7:00pm: Registration, Food, Networking

7:00pm-8:00pm: Talk

8:00pm-8:30pm: Q&A and Networking

Cost:

FREE for IEEE members

Suggested donations to cover food and water (pay at door):

Non-IEEE: $5

Students (non-IEEE): $3

Online registration is recommended to guarantee seating

DIS Talk Abstract:

With resurgence of AI and machine learning, sensor miniaturization and increased wireless connectivity, ear-level devices are going through a major revolution transforming themselves from hearing devices into hearing enhancement and health and wellness monitoring devices. In this talk, we will present examples of such transformation in the areas of hearing enhancement, health and wellness monitoring and user experience. In the process, we will highlight how AI and machine learning, miniaturized sensors and wireless connectivity are enabling and accelerating the transformation. In addition, we will discuss practical challenges for the transformation today. Finally, we will provide an outlook on future directions and opportunities.

DIS Speaker Biography:

Tao Zhang received his B.S. degree in physics from Nanjing University, Nanjing, China in 1986, M.S. degree in electrical engineering from Peking University, Beijing, China in 1989, and Ph.D. degree in speech and hearing science from the Ohio-State University, Columbus, OH, USA in 1995. He joined the Advanced Research Department at Starkey Laboratories, Inc. as a Sr. Research Scientist in 2001, managed the DSP department from 2004 to 2008 and the Signal Processing Research Department from 2008 to 2014. Since 2014, he has been Director of the Signal Processing Research department at Starkey Hearing Technologies, a global leader in providing innovative hearing technologies. He has received many prestigious awards including Inventor of the Year Award, the Mount Rainier Best Research Team Award, the Most Valuable Idea Award, the Outstanding Technical Leadership Award and the Engineering Service Award at Starkey.

He is a senior member of IEEE and the Signal Processing Society and the Engineering in Medicine and Biology Society. He serves on the IEEE AASP Technical Committee, the industrial relationship committee and the IEEE ComSoc North America Region Board. He is an IEEE SPS Distinguished Industry Speaker and the Chair of IEEE Twin-cities Signal Processing and Communication Chapter.

His current research interests include audio, acoustic, speech signal processing and machine learning; multimodal signal processing and machine learning for hearing enhancement, health and wellness monitoring; psychoacoustics, room and ear canal acoustics; ultra-low power real-time embedded system design and device-phone-cloud ecosystem design. He has authored and coauthored 120+ presentations and publications, received 20+ approved patents and had additional 30+ patents pending.


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