IEEE Computer Society
Santa Clara Valley

  • About IEEE CS SCV

    The IEEE Computer Society of Silicon Valley is the largest Chapter in the area. We operate as part of the global IEEE Computer Society, which with nearly 85,000 members, is the world’s leading organization of computing professionals. IEEE CS was founded in 1946, and is the largest of the IEEE’s 38 societies. The Computer Society is dedicated to advancing the theory and application of computing and information technology.
    Our Santa Clara Valley Chapter emphasizes all aspects of computing to our local members, and we welcome visitors. We organize monthly Technical Meetings, which give opportunity for professional networking, and where invited speakers from the industry share their vision on the computing domain.
    During early summer, the Chapter also organizes its own low-cost, high value, New Frontiers In Technology (NFIC) conference.

GPU Computing: Taming a 23,000 Thread Beast!

Past event: September 13, 2011

This event is available on demand:

Co sponsors:

IEEE Signal Processing Society 

Speaker: Michael Shebanow, Ph. D., Principal Research Scientist, NVIDIA 


GPUs have fundamentally changed the playing field of high performance computing. Starting out as devices intended only for the display of 3D images, GPUs are now used as supercomputers – attached processors used to accelerate computationally intensive applications. In this talk, using NVIDA GPUs as a basis, I’ll provide a brief history of the GPU, the evolution of GPUs into computing devices, understanding their performance characteristics, and the challenges that lie attaining high performance from these devices. 


Michael Shebanow joined NVIDIA in 2003. While at NVIDIA, he has worked on the Tesla product family (G80, GeForce 68xx series) and was one of the lead architects of the Fermi (GF100) family. Also for Fermi, he managed the shader processor architecture team (covered 5 blocks including the SM & L1). He is currently in the research group investigating next generation graphics and unified programming models for GPUs. Prior to NVIDIA, he has managed the development of a number of processors in multiple architecture families (x86-32, x86-64, SPARC v9, 68k, m88k), and was one of three representatives representing Motorola in the Power PC architecture definition committee. While a graduate student at UC Berkeley, he was one of the original developers of HPS (superscalar, dynamically scheduled processor architectures) (started 1984). Dr. Shebanow holds 25 patents in graphics, processor design, and disk controller areas.


Thanks to those sponsoring part of our pizza this meeting:

  • KLOOBOK LLC, offering Maze, a Linux tool for testing and debugging concurrent applications. Put your multicore program through maze.
  • NVIDIA: The engine of computer graphics.


Media coverage


Presentation slides:

Taming a 23000 Thread Beast

On-demand webinar

This event can be viewed as an on-demand webinar at this link (requires Silverlight)








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