IEEE Computer Society
Santa Clara Valley
IEEE

  • About IEEE CS SCV

    The IEEE Computer Society of Silicon Valley is the largest Chapter in the area. We operate as part of the global IEEE Computer Society, which with nearly 85,000 members, is the world’s leading organization of computing professionals. IEEE CS was founded in 1946, and is the largest of the IEEE’s 38 societies. The Computer Society is dedicated to advancing the theory and application of computing and information technology.
    Our Santa Clara Valley Chapter emphasizes all aspects of computing to our local members, and we welcome visitors. We organize monthly Technical Meetings, which give opportunity for professional networking, and where invited speakers from the industry share their vision on the computing domain.
    During early summer, the Chapter also organizes its own low-cost, high value, New Frontiers In Technology (NFIC) conference.

SPARC 3.6 GHz Processor: a 16-core 128 threaded SoC

Jason M. Hart

SPARC 3.6 GHz Processor:

a 16-core, 128 threaded SoC

Date: Tuesday, August 13, 2013

Speaker: Jason Hart, Oracle

Time: 6:30 PM (PT) Networking/Refreshments, 7:00 PM Presentation

Registration: Please register by ordering a ticket below

Location: Cadence / Bldg 10, 2655 Seely Ave, San Jose, CA (map)

Abstract

The 3.6 GHz T5 processor is Oracle’s next- generation CMT SPARC processor implemented in TSMC’s 28nm process with 1.5 billion transistors. Significant performance improvements were made by doubling the previous generation’s number of cores to 16 and L3 cache size to 8 MB while increasing bandwidth by nearly 3x. Power efficiency was improved through features like DVFS, core pair cycle skipping and SerDes power scaling.

This presentation will give a brief summary of the processor and core architecture and features. The physical composition will be covered including the library cell swapping and characterization methodologies. A look at the new power management features will be followed by power distribution and clock distribution, including a look at the frequency-locked loop and clock multiplexor. We will look at the L3 cache and its repair mechanisms. Then we will conclude with the SerDes Wide Band Amplifier.
Download presentation HERE

Stream Presentation [Requires MS Silverlight]

Speaker Bio

Jason Hart received the B.S. degree in electrical engineering from the University of Idaho, Moscow. He joined Sun Microsystems, Inc. in 1995 after working in Product Engineering at Micron Technology, Boise, ID. Jason has been doing circuit design, global circuits and composition for UltraSPARC I, III, IV+ and now Oracle’s T5. Design work has included SRAM’s, register files, static and dynamic custom circuits, libraries, timing, FGU composition, and responsibility for clocking on T5.

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