Santa Clara Valley-San Francisco Chapter of Electron Devices Society (Silicon Valley, California)



Welcome to Electron Devices Society–Santa Clara Valley/San Francisco Chapter


IEEE EDS Distinguished Lecturer Talk

Title: Spintronics-Perspectives and Challenges

Speaker: Prof. Brajesh Kumar Kaushik, IIT

Tuesday, March 5, 2019 at 6:00PM
Texas Instruments Conference Center
2900 Semiconductor Dr, Building E, Santa Clara, CA 95051


Conventional CMOS technology has reached to the brink of its scaling limits and poses significant challenges for the development of next generation high-speed ultra-low power cost-effective memory and processing devices. The failure of Moore’s law on the technology roadmap has enforced the research community to explore alternative technology solutions to mitigate the problems. In the post-CMOS era, spintronics shall emerge as a potentially viable interdisciplinary field with credible technological perspectives. Spintronic exploits an electron’s spin orientation and its associated magnetic moment as a state variable instead of a conventionally used charge in CMOS technology. In general, the spintronic devices are layered structure of ferromagnetic materials and provide the nonvolatile storage options and manipulations of logic states. Spin transfer torque (STT) and spin orbit torque (SOT) devices using magnetic tunnel junctions (MTJs) have become strong contenders for the nonvolatile embedded memory architectures with the capability of implementing the concepts of “logic-in-memory” and “material-device-circuit co-design.” The spin torque devices offer the features of “universal memory” i.e., high speed, nonvolatility, high density, and low power, high endurance, CMOS process compatibility. Apart from the basic spin torque devices, the field of spintronics encloses all spin logic (ASL) devices, domain wall (DW) based devices, spin diodes, and spin FETs. The material and device level roadmaps for the field of spintronics suggest that the research work is at the infant stage and still require different elemental spin device developments with the understanding of associated underlying physics. In addition, the accurate models for the spintronic devices imitating the effect of stochastic behaviour and PVT variations need to be explored. Spintronics based architectures are being considered for computing applications such as bio-inspired computing and quantum computing. These spintronics based novel computing approaches find applications in image processing and provides efficient solution to the complex computing problems.

Speaker Biography
Brajesh Kumar Kaushik received his Doctorate of Philosophy (Ph.D.) in 2007 from Indian Institute of Technology, Roorkee, India. He joined Department of Electronics and Communication Engineering, Indian Institute of Technology, Roorkee, as Assistant Professor in December 2009; and since April 2014 he has been an Associate Professor. He has served as General Chair, Technical Chair, and Keynote Speaker of many reputed international and national conferences. Dr. Kaushik is a Senior Member of IEEE and member of many expert committees constituted by government and non-government organizations. He is Associate Editor of IET Circuits, Devices & Systems; Editor of Microelectronics Journal, Elsevier; Editorial board member of Journal of Engineering, Design and Technology, Emerald; and Editor of Journal of Electrical and Electronics Engineering Research, Academic Journals. He also holds the position of Editor-in-Chief of International Journal of VLSI Design & Communication Systems, and SciFed Journal of Spintronics & Quantum Electronics. He has received many awards and recognitions from the International Biographical Center (IBC), Cambridge. His name has been listed in Marquis Who’s Who in Science and Engineering® and Marquis Who’s Who in the World®. Dr. Kaushik has been conferred with Distinguished Lecturer award of IEEE Electron Devices Society (EDS) to offer EDS Chapters with quality lectures in his research domain. His research interests are in the areas of high-speed interconnects, low-power VLSI design, memory design, carbon nanotube-based designs, organic electronics, FinFET device circuit co-design, electronic design automation (EDA), spintronics-based devices, circuits and computing, image processing, and optics & photonics based devices.


More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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