Santa Clara Valley-San Francisco Chapter of Electron Devices Society (Silicon Valley, California)



Welcome to Electron Devices Society–Santa Clara Valley/San Francisco Chapter

Materials, Devices, and Modeling of Advanced Semiconductor Devices – An IEEE EDS Distinguished Lecturer Double-Header
Friday, Nov 30, 2018 at 11:30AM
Texas Instruments Conference Center
2900 Semiconductor Dr, Building E, Santa Clara, CA 95051
11:30AM-noon – Pizza and networking
12 PM – Are Extended Defects a Show Stopper for Future III-V CMOS Technologies, Cor Claeys, KU Leuven
12:30PM – Modeling and Simulation of FinFET and Nanosheet Transistors for Advanced Technology Nodes, Yogesh Chauhan, IIT Kanpur
1PM – Informal interactions/off-line Q&A with speakers
Talk 1: Are Extended Defects a Show Stopper for Future III-V CMOS Technologies, Cor Claeys, KU Leuven
The progress in epitaxial growth techniques resulted in intensive research on the potential use of non-Si based substrates, enabling the fabrication of Ge (p-channel), III-V (n-channel) or hybrid Ge/III-V devices on a Si substrate. These high mobility materials are also implemented in TFET and nanowire structures. Heterogenous integration of Ge and III-V technologies on a silicon platform enables to fabricate System-on-Chip applications and has potential for Internet-of-Things (IoT) applications. The aspect-ratio-trapping (ART) heteroepitaxy technique is successfully applied for the fabrication of non-planar devices like for Gate-All Around structures, FinFETs and TFETs. Due to the lattice mismatch between Si and the device layer (Ge or III-V), the challenge is to suppress or minimize the formation of
misfit and threading dislocations.
First a review is given of some of the present-day state-of-the art III-V devices processed on a Si platform reported in the literature, before addressing defect engineering aspects for III-V processing on a Si-platform from both a structural and electrical performance perspective. The identification of the extended defects will be illustrated by some case studies based on Deep Level transient Spectroscopy (DLTS) analysis and low frequency noise spectroscopy. Information on the basic defect parameters can be used as input for TCAD simulation of the electrical device performance, enabling a further optimization of the materials’ growth and
process conditions. The optimal goal is to determine for real devices the tolerable defect levels without penalizing their performance.
Cor Claeys is Professor at the KU Leuven (Belgium) since 1990. He was with imec, Leuven, Belgium from 1984 till 2016. His main interests are semiconductor technology, device physics, low frequency noise phenomena, radiation effects and defect engineering. He co-edited books on “Low Temperature Electronics” and “Germanium-Based Technologies: From Materials to Devices” and wrote monographs on “Radiation Effects in Advanced Semiconductor Materials and Devices”, “Fundamental and Technological Aspects of Extended Defects in Germanium” and “Random Telegraph Signals in Semiconductor Devices” and “Metals in Silicon- and Germanium-Based Technologies: Origin, Characterization, Control and Electrical Impact”. Two books are translated in Chinese. He (co)authored 14 book chapters, over 1100 conference presentations and more than 1300 technical papers. He is editor/co-editor of 60 Conference Proceedings. Prof. Claeys is a Fellow of the Electrochemical Society and of IEEE. He was Founder of the IEEE Electron Devices Benelux Chapter, Chair of the IEEE Benelux Section, elected Board of Governors Member and EDS Vice President for Chapters and Regions. He was EDS President in 2008-2009 and Division Director on the IEEE Board of Directors in 2012-2013. He is a recipient of the IEEE Third Millennium Medal and received the IEEE EDS Distinguished Service Award. Within the Electrochemical Society, he was Chair of the Electronics & Photonics Division (2001-2003) . In 2004, he received the Electronics & Photonics Division Award. In 2016 he received the Semi China Special Recognition Award for outstanding involvement in the China Semiconductor Technology International Conference (CSTIC).
Talk 2: Modeling and Simulation of FinFET and Nanosheet Transistors for Advanced Technology Nodes, Yogesh Chauhan, IIT Kanpur
Continued scaling of transistors has forced us to scale the channel thickness of the device to have strong electrostatic control and get rid of the short channel effects. The reduced channel thickness results in the confinement of charge carriers and larger quantization effect. In addition to the scaling, alternative channel materials having better transport properties are also being explored to boost the device performance. The promising options for channel materials in post Si era are Ge, SiGe, III-V and 2D layered semiconductors. The III-V semiconductor materials have lower effective mass and as a consequence lower density of states (DOS). The lower DOS introduces a new capacitance component in gate capacitance in addition to the existing charge centroid and gate oxide capacitance and is called as quantum capacitance. Scaling has also resulted in channel lengths of modern and upcoming devices to be comparable to the mean scattering lengths of the semiconductor material. This causes some of the charge carriers to travel from the source to the drain without any significant scattering. Therefore, the generic principles governing the drift-diffusive framework, i.e. (i) the concept of mobility, and (ii) local field dependent velocity, are no longer valid. This quasi-ballistic transport results in significant deviation from the device behaviour predicted by traditional drift diffusive models. Since different carriers experience different amounts of scattering, modeling such devices is not only interesting but also challenging. In this talk, I will discuss the physics and modelling of different quantum effects and transport in extremely scaled transistors with different channel materials.
Yogesh Singh Chauhan is an associate professor at Indian Institute of Technology Kanpur (IITK), India. He was with Semiconductor Research & Development
Center at IBM Bangalore during 2007 – 2010; Tokyo Institute of Technology in 2010; University of California Berkeley during 2010-2012; and ST Microelectronics during 2003-2004. He is the developer of industry standard BSIM-BULK (formerly BSIM6) model for bulk MOSFETs and ASM-HEMT model for GaN HEMTs. His group is also involved in developing compact models for FinFET, Nanosheet/Gate-All-Around FET, FDSOI transistors, Negative Capacitance FETs and 2D FETs.

He is the Editor of IEEE Transactions on Electron Devices and Distinguished Lecturer of the IEEE Electron Devices Society. He is the member of IEEE-EDS Compact Modeling Committee and fellow of Indian National Young Academy of Science (INYAS). He is the founding chairperson of IEEE Electron Devices Society U.P. chapter and Vice-chairperson of IEEE U.P. section. He has published more than 200 papers in international journals and conferences. He received Ramanujan fellowship in 2012, IBM faculty award in 2013 and P. K. Kelkar fellowship in 2015, CNR Rao faculty award and Humboldt fellowship in 2018. His research interests are characterization, modeling, and simulation of semiconductor devices. He has served in the technical program committees of IEDM, SISPAD, ESSDERC, EDTM, and VLSI Design conferences.


(The following seminar is co-sponsored by IEEE EPS Chapter.)


Improving the IEEE: Issues, Ideas, Best Practices

Moderator: Dr. Renuka Jindal, Director, IEEE Division I, Eminent Scientist and Chief Technology Officer, Vanderziel Institute of Science and Technology, LLC.

When: Saturday, December 1, 2018, 2:00 – 4:00 PM

Where: Santa Clara University (Benson 21), Santa Clara



This will be an event “for listening to” engineers and managers in Silicon Valley who have ideas for improving the IEEE, or have issues they’d like to raise. With input and grass-roots suggestions for improving the IEEE, I intend to provide actionable feedback at the IEEE TAB and BOD level. Your input will be critical in shaping the future of the IEEE and will need your active support to make this a reality.
If you wish to bring specific thoughts about IEEE changes, improvements and growth, be prepared to present them to the group for, say, 5 minutes, for discussion and enhancement. The meeting secretary will take notes, along with any handouts you provide, and ask for others who would like to be further involved with your specific suggestion. Renuka will receive your inputs and the summary, and is taking steps to allow him to gather world-wide input on these specific ideas that can inform and support the issues that are raised by our SV community of entrepreneurs.

Speaker Biography

Dr. Renuka Jindal’s technical focus has been on research and teaching in the theory and practice of random processes applicable to a wide variety of phenomena in electronic and photonic devices and circuits, lightwave and wireless communications and biological systems. He was with Bell Labs at Murray Hill, Princeton and Whippany, NJ as a distinguished member of technical staff for 22 years, bridging both technical and administrative roles. Highlights include his pioneering work in developing a physical understanding of noise in MOS devices with few hundred nanometers regime channel lengths and ultra-low noise amplification of fiber-optic signals. Until recently, he has served as Professor of Electrical and Computer Engineering, University of Louisiana at Lafayette.
As a 41 year veteran of IEEE with a dual career in industry and academia, Dr. Jindal rose through the ranks as Editor, Editor-in-Chief, VP of Publications, and as EDS president in 2010-2011, and now serves as Director of IEEE Division I, sitting on the IEEE Board. As EDS president he formulated the vision and mission of EDS, enhancing member benefits and launching a plethora of initiatives reversing the decline in EDS membership. He brought together 6 societies and 1 council to launch the highly successful IEEE Journal of Photovoltaics, mushrooming IEEE’s share in the PV space. He Launched the EDS webinar series serving the practicing engineer, now considered a best practice in IEEE. And he Launched the 1st EDS OPEN ACCESS Journal J-EDS. He is also a recipient of the IEEE 3rd Millennium medal.





More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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