Santa Clara Valley-San Francisco Chapter of Electron Devices Society

IEEE

Home

In early December, there will be 3 Distinguished Lecturer seminars. Please find details below.

Please note that the dates and locations are NOT the same as our regular monthly seminars.

 

Please register here

 

************************************************************************************

************************************************************************************

************************************************************************************

 

December 5:

 

IEEE SCV-SF Electron Devices Society Seminar “Nano-Material Engineered Interconnect Technologies for Heterogeneous System Integration”

Prof. Mansun Chan, Hong Kong University of Science & Technology

An IEEE-EDS Distinguished Lecture

Time: 6:00 PM – 8:00 PM;  (Talk will start around 6:15pm)
Date: Dec. 5, 2017; (Tuesday)
Room: Rotunda Room;
Building: Guadalupe Hall, Santa Clara University;
Address: 455 El Camino Real, Santa Clara, CA


Nano-Material Engineered Interconnect Technologies for Heterogeneous System Integration

Mansun Chan

 

Dept. of ECE, Hong Kong University of Science & Technology,

Clear Water Bay, Kowloon, Hong Kong

E-mail: mchan@ust.hk

 

Abstract: The scaling of CMOS has encountered many hurdles in the sub-10nm technology nodes as we are approaching the end of the Moore’s Law. The performance limitations have shifted to the interconnect technology to reduce the metal wire resistance as well as the k-value of the interlayer dielectrics. The popular interconnect materials such as copper and tungsten have been found to be insufficient due to increasing resistivity with dimension scaling and electromigration concern under high current density. And using porous structures to form the interlayer dielectrics is subjected to the weakening of the mechanical strength of the dielectric film. New materials such as carbon nanotube (CNT) and graphene have been extensively studied to extend the scaling roadmap for interconnects. However, many barriers have to be overcome before these materials can enter mainstream manufacturing. In this presentation, I am going to present some of the recent progresses in using CNT as a contact plug as well as an agent to form very low k-value interlayer dielectrics.

 

Biography:

Prof. Mansun Chan received his BS in Electrical Engineering and Compute Science with highest honors from the University of California at San Diego and then completed his MS and PhD at the University of California at Berkeley. At Berkeley, was one of the major contributors to the unified BSIM model for SPICE, which has been accepted by most US companies and the Compact Model Council (CMC) as the first industrial standard MOSFET model. Subsequently, he joined the Electrical and Electronic Engineering Department at Hong Kong University of Science and Technology. His research interests include emerging nano-device technologies, 2-D device for flexible electronics, Artificial Neural Network devices and applications, new-generation memory technology, BioNEMS, device modeling and ultra-low power circuit techniques. Between July 2001 and December 2002, he was a Visiting Professor at University of California at Berkeley and the Co-director of the BSIM program. He is currently still consulting on the development of the next generation compact models.

Prof. Chan has been actively contributing to the professional community and hold many positions. He is a Board of Governor, Chair of the Education Committee, the Chair of the Region 10 subcommittee and a Distinguished lecturer of the IEEE Electron Device Society. He has also chaired many international conferences and acting as editors for a number of technical journals. In addition, he has received many awards including the UC Regents Fellowship, Golden Keys Scholarship for Academic Excellence, SRC Inventor Recognition Award, Rockwell Research Fellowship, R&D 100 award (for the BSIM3v3 project), Distinguished Teaching Award, the Shenzhen Science and Technology Innovation awards etc. He is a Fellow of HKIE, IET and IEEE.

 

 

*************************************************************************************

*************************************************************************************

*************************************************************************************

 

December 8:

 

IEEE SCV-SF Electron Devices Society Seminar “2D Electronics — Opportunities and Challenges”

Prof. Frank Schwierz, TU Ilmenau

An IEEE-EDS Distinguished Lecture

Location: Packard Building 101, Stanford University

Date: Friday December 8, 4:00 PM

Parking information: 

https://transportation.stanford.edu/parking/about-parking-permits/view-parking-and-circulation-map

Visitors should park in the Via Ortega Garage, the Roble Field Garage, or the Roth Way Garage (in that order of preference) and parking is FREE after 4pm. (This is one of the reasons for having the seminar at that time.)

 

Abstract: During the past decade, 2D (two-dimensional) materials have attracted enormous attention from various scientific communities ranging from chemists and physicists to material scientists and device engineers. The rise of the 2D materials began in 2004 with the work on graphene done at Manchester University and Georgia Tech. Particularly the observed high carrier mobilities raised early expectations that graphene could be a perfect electronic material. It soon became clear, however, that due its zero bandgap graphene is not suitable for most electronic devices, in particular transistors. On the other hand, researchers have extended their work to 2D materials beyond graphene and the number of 2D materials under investigation is continuously rising. Many of them possess sizeable bandgaps and therefore are considered to be useful for transistors. Indeed, the progress in the field of 2D transistors has been rapid and experimental MOSFETs using semiconducting 2D channel materials have been reported by many groups. A recent achievement was the demonstration of a well-performing 1-nm gate MoS2 MOSFET in 2016. On the other hand, and in spite of the progress in the field, the debate on the real prospects of the 2D materials for future electronics is still controversial.

In the present lecture, the most important classes of 2D materials are introduced and the potential of 2D transistors is assessed as realistically as possible. To this end, two material properties – bandgap and mobility – are examined in detail and the mobility-bandgap tradeoff is discussed. The state of the art of 2D transistors is reviewed by summarizing relevant results of leading groups in the field, presenting examples of the lecturer’s own work on 2D electronics, and comparing the performance of 2D transistors to that of competing conventional transistors. Based on these considerations, a balanced view of both the pros and cons of 2D transistors is provided and their potential in both the More Moore (digital CMOS) and the More Than Moore domains of semiconductor electronics is discussed. It is shown that due to the rather conservative CMOS scaling scenario of the 2015 ITRS (compared to the more aggressive scenarios of the previous ITRS editions) it will be difficult for 2D materials to make inroads into mainstream CMOS. However, due to their specific properties (for example, 2D materials are bendable and stretchable) they may enable entirely new applications in the More Than Moore domain.

 

Bio: Frank Schwierz received the Dr.-Ing. and Dr. habil. degrees from Technische Universität (TU) Ilmenau, Germany, in 1986 and 2003, respectively. Presently he serves as Privatdozent at TU Ilmenau and is Head of the RF & Nano Device Research Group. His research interests include semiconductor device physics, novel device and material concepts for future transistor generations, and high-performance radio frequency transistors. At present he is particularly interested in two-dimensional electronic materials.

Dr. Schwierz is conducting research projects funded by the European Community, German government agencies, and the industry. Together with partners from academia and industry he was involved in the development of the fastest Si-based transistors worldwide in the late 1990s, of Europe’s smallest MOSFETs in the early 2000s, as well as of the fastestGaN HEMTs on Si and the fastest GaN tri-gate HEMTs worldwide in the 2010s. His recent work on two-dimensional materials made a major contribution to the current understanding of the merits and drawbacks of graphene transistors.

Dr. Schwierz has published more than 260 journal and conference papers including 40 invited papers. He is author of the books Modern Microwave Transistors – Theory, Design, and Performance (J. Wiley & Sons 2003) and Nanometer CMOS (Pan Stanford Publishing 2010) and editor of the book Two-Dimensional Electronics – Prospects and Challenges (MDPI 2016).

Dr. Schwierz is Senior Member of the IEEE. He serves as a Distinguished Lecturer of the IEEE Electron Devices Society and as an editor of the IEEE Transactions on Electron Devices. Moreover, he is one of the key contributors to the Emerging Research Devices Technology Working Groups of the 2013 and 2015 ITRS editions.

 

************************************************************************************

************************************************************************************

************************************************************************************

 

December 6:

 

IEEE SCV-SF Electron Devices Society co-sponsored workshop

“10th MOS-AK Compact Modeling Workshop in the Silicon Valley”

Time: December 6, 2017

Location: Cadence Office; Silicon Valley

Synopsis: The MOS-AK Association is organizing 10th successive compact modeling workshop in the timeframe of the IEDM and CMC Meetings on Dec.6, 2017 in Silicon Valley. The MOS-AK workshops are open HiTech forums to discuss the frontiers of electron device modeling with emphasis on simulation-aware models. MOS-AK Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and its Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all the important aspects of compact model development, implementation, deployment and standardization within the main theme – frontiers of the compact modeling for nm-scale MEMS designs and CMOS/SOI circuit simulations.

 

Topics: to be covered include the following:
• Advances in semiconductor technologies and processing
• Compact Modeling (CM) of the electron devices
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• FOSS TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, TFT CMOS and SOI-based memory cells
• Organic, Bio/Med devices/technology modeling
• Microwave, RF device modeling, HV/Power device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and IC Designs
• Foundry/Fabless Interface Strategies

Online registration:
http://www.mos-ak.org/silicon_valley_2017

 

FOSS TCAD/EDA tools for advanced nano-device modeling
Wladek Grabinski
MOS-AK (EU)

Abstract:
Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes; thru the MOSFET, FDSOI, FinFET and TFET compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present two FOSS CAD simulation and design tools: ngspice and Qucs. Application and use of these tools for advanced IC design (e.g. analog/RF IC applications) directly depends the quality of the compact models implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the transistor level and then trigger further discussion on the compact/SPICE model Verilog-A standardization and development supporting FOSS CAD tools.

 

Biography:
Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, Poland, in 1991. From 1991 to 1998 he was a Research Assistant at the Integrated Systems Lab, ETHZ, Switzerland, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPFL, and was engaged in the compact MOSFET model developments supporting numerical device simulation and parameter extraction. Later, he was a technical staff engineer at Motorola, and subsequently at Freescale Semiconductor, Geneva Modeling Center, Switzerland. He is now an consultant responsible for modeling, characterization and parameter extraction of MOST devices for the IC design. He is currently consulting on the development of next-generation compact models for the nanoscaled technology very large scale integration (VLSI) circuit simulation. His current research interests are in high frequency characterization, compact modeling and its Verilog-A standardization as well as device numerical simulations of MOSFETs for analog/RF low power IC applications. He is an editor of the reference modeling book Transistor Level Modeling for Analog/RF IC Design and also authored or coauthored more than 50 papers. Wladek is the chair of the ESSDERC Track4: “Device and circuit compact modeling” as well as has served as a member of organization committee of ESSDERC/ESSDERC, TPC of SBMicro, SISPAD, MIXDES Conferences; reviewer of the IEEE TED, IEEE MWCL, IJNM, MEE, MEJ. He is a Member At Large of Swiss IEEE ExCom and also supports the EPFL IEEE Student Branch acting as its Interim Branch Mentor. Wladek is involved in activities of the MOS-AK Association and serves as a coordinating manager since 1999.

 

**************************************************************************

 


More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

Subscribe or Invite your friends to sign up for our mailing list and get to hear about exciting electron-device relevant talks. We promise no spam and try to minimize email. You can unsubscribe easily.
http://sites.ieee.org/scv-eds/subscribe/

Follow us on social media

fb_icon_325x325 twitter_logo1-copy-256x256 256px-linkedin-svg_2 google-plus-logo-red-265px meetup