Santa Clara Valley-San Francisco Chapter of Electron Devices Society (Silicon Valley, California)



Welcome to Electron Devices Society–Santa Clara Valley/San Francisco Chapter


IEEE EDS August Seminar

Title: Doping profile control via oxygen-insertion silicon channel and its benefit of device performance

Speaker: Hideki Takeuchi, Atomera Inc.

Tuesday, August 13, 2019 at 6:00PM

Texas Instruments Conference Center
2900 Semiconductor Dr, Building E, Santa Clara, CA 95051


Interstitial trapping by OI (oxygen-inserted) silicon channel results in blocking of boron and phosphorus TED (transient enhanced diffusion) as well as retention of channel boron profiles during the gate oxidation process. The OI layers are also beneficial for achieving USJ (ultra-shallow junctions) with low sheet resistance (Rsh) formed by high-dose implantation and rapid thermal annealing because they reduce dopant diffusion away from the surface and can provide for higher levels of active dopant concentration. The enhanced doping profile control capability is applicable to punch-through stop of advanced CMOS devices and its benefits to 28 nm planar CMOS and bulk FinFET devices projected by TCAD are discussed.

Speaker Biography
Hideki Takeuchi is Director of MST Integration at Atomera Inc. He received M.E. degree at University of Tokyo in 1990. From 1997 to 2005, he worked as research staff in Semiconductor Device group at UC-Berkeley and was involved in various research activities such as fabrication and characterization of proto-type FinFET devices, HKMG material and processing, non-volatile memories, RF-MEMS, and so forth. He has been with Atomera Inc. (formerly, Mears Technologies Inc.) since 2008, and is currently in charge of process integration of the OI silicon technology (aka MSTTM).


More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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