Santa Clara Valley-San Francisco Chapter of Electron Devices Society (Silicon Valley, California)



Welcome to Electron Devices Society–Santa Clara Valley/San Francisco Chapter

(The following seminar is co-sponsored by SFBA Nanotechnology Council.)


Connecting Atomic Level Material Analysis to Transistor Scale Modeling for FinFET and Nanowire Design

Victor Moroz

Fellow, Synopsys

Tuesday, October 9, 2018 @ 6PM

Texas Instruments Conference Center
2900 Semiconductor Dr, Santa Clara, CA 95051

Cost to attend: FREE

Contact: Peter Rabkin,

6:00PM: Free Pizza
6:15PM: Talk


At 5nm design rules, atomic scale effects kick in on several levels: the bandstructures of Si and SiGe fins deviate from bulk properties, impacting transistor performance by about 10%. Further scaling makes transistor behavior even more sensitive to atomic scale changes in critical layer thicknesses, including fin/nanowire thickness changes as the current flows from source to channel and from channel to drain. We also explore different types of surface roughness due to plasma etch and lithography line edge roughness and its impact on transistor behavior. Quantum transport analysis suggests very non-intuitive engineering of surface roughness that can be transparent to the current flow for certain surface roughness patterns. The emerging role of atomic scale and quantum transport effects indicate a paradigm shift towards bandstructure driven transistor design. A key side effect of this is that the choice between different transistor architectures will come down to imperfections of different architectures and how these imperfections can be controlled and mitigated in high volume manufacturing environment. Atomic scale effects are inherently difficult to capture and quantify experimentally. Therefore, we use rigorous ab-initio physical approach to characterize such effects and extract guidelines for the future transistor design.

Speaker Biography

Victor Moroz received Ph.D. degree in Applied Physics from the University of Nizhny Novgorod in 1992 and joined a Stanford spin-off Technology Modeling Associates in 1995, which later became a part of Synopsys, connecting a design company to the manufacturing.
Currently Dr. Moroz is a Synopsys Fellow and Editor of Electron Device Letters, engaged in a variety of projects on analysis of advanced CMOS technology. Several facets of this activity are reflected in 100+ publications and 100+ granted and pending US patents.





More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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