Santa Clara Valley-San Francisco Chapter of Electron Devices Society

IEEE

Co-sponsored Events

Co-sponsored Events:
November 2017: 

Date: Tuesday, November 7, 2017
Time: 8:30 am – 3:30 pm (PT) (Lunch will be provided)
Location: Xilinx, 2050 Logic Drive, San Jose CA (Map: goo.gl/maps/V7GpFxFH8u72)
Attendance: On-site or Remote (WebEx)
Cost: none

Registration:

9th Annual IEEE CPMT SCV Soft Error Rate (SER) Workshop – SCV Chapter, IEEE CPMT Society

EDS/EPS/Reliability Chapter Workshop 
9th Annual IEEE Soft Error Rate (SER) Workshop
    — tutorials, alpha upset, materials selection, process control, case studies … 
    — Co-sponsored by: Electron Devices, Electronics Packaging and Reliability Chapters 
    — No cost (includes lunch); Tues, Nov 7, at Xilinx, San Jose (or via WebEx) 
This local Workshop addresses alpha-induced soft errors in computers, routers, memory, etc, and offers simultaneous on-site and remote participation for presentations and interactive discussions on a variety of critical subjects on SER for an ever-increasing international audience. For this year’s event, we have invited two industry experts in the field to offer tutorials on fundamentals of soft errors and their impact on applications, as well as experimental approaches.
  8:30 AM: Introduction 
Two morning tutorials: 
  8:45 AM: Tutorial: “Single Event Effects” (Austin Lesea, Xilinx)
  9:25 AM: Tutorial: “Probability and Statistics for Experimenters” (Gary Swift, Swift Engineering)
Talk Titles: 
  10:00 AM: “Study of the Alpha Counts from Solder Bump Material at Elevated Temperature and Introduction of Advanced-Grade Material” (Hirotaka Hirano, Mitsubishi Materials) 
  10:45 AM: “Assessment of Alpha Particle Susceptibility of Product Chips Through Accelerated Tests” (Paul Muller, IBM)
  11:25 AM: “Opportunities at the Stanford Underground Research Facility” (Jaret Heise, Stanford Underground Research Facility) 
  12:00 noon: Lunch (provided) 
  1:00 PM: “Practical Aspects of Realtime Testing” (Jeff Barton and Eric Crabill, Xilinx)
  1:45 PM: “New High Energy Neutron Spallation Beam, ChipIr at Appleton-Reutherford Lab at Oxford” (Francis Classe, Cypress) 
  2:25 PM: “On the Efficacy of Using Proton Beams For Estimating Neutron-Induced Soft Error Rates” (Norbert Seifert, Intel) 
  3:15 PM: Closing and Dismissal 
Registration is now open, and there is no cost — sign up for either on-site participation, or attending via WebEx. 9th Annual IEEE CPMT SCV Soft Error Rate (SER) Workshop – SCV Chapter, IEEE CPMT Society

 

 

 

July 2017
July 20th, 2017 Energy Efficient Computing in Nanoscale CMOS

Sponsored by: IEEE Santa Clara Valley Solid State Circuits Society, Co-sponsored by IEEE Electron Devices Society SCV Chapter

Time: July 20th, 2017, 6:00 PM to 8:00 PM

Speaker: Dr. Vivek De, Intel Fellow and Director of Circuit Technology Research at Intel Labs

Location: Texas Instruments Auditorium (Building E Visitor Center), 2900 Semiconductor Dr, Santa Clara, CA 95051

Seminar Program

October 2016
Nov 3rd, 2016 CPI stress induced carrier mobility shift in advanced silicon nodes Sponsored by: IEEE SCV Reliability Chapter, Co-sponsored by IEEE Electron Devices Society SCV Chapter

Time: Thursday, Nov 3, 2016,  6:00 PM to 8:00 PM

Speaker: Dr. Valeriy Sukharev, Technical Lead at the Design to Silicon Division (Calibre) of Mentor Graphics Corporation

Location:

Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051 (Meeting will be in the cafeteria, Building B)

Seminar Program

June 2016
June 21st, 2016 Transforming Nanodevices to Nanosystems Sponsored by: IEEE SF Bay Area Nanotechnology Council, Co-sponsored by IEEE Electron Devices Society SCV Chapter

Time: Tuesday, June  21st, 2016, 11:30 am- 1:00 pm

Speaker: Max M. Shulaker, Stanford University

Location:

Texas Instruments (TI) Auditorium E-1
2900 Semiconductor Drive
Santa Clara, CA

Seminar Program

May 2013
May 7th, 2013 Semiconductor Laser Reliability and Failure AnalysisSponsored by: IEEE Photonics Society Santa Clara Valley ChapterCo-sponsored by IEEE Electron Devices Society SCV Chapter and IEEE Reliability Society SCV Chapter

Time: Tuesday, May 7th, 2013, 6pm-8:30pm

 

Speaker: Dr. Robert W. Herrick, INTEL

 

Location:

Cogswell College (N.B. New Location–“Dragon’s Den” rm.)

1175 Bordeaux Dr, Sunnyvale, CA 94089

(Location: Between Moffett Park Drive and Java Drive)
Seminar Program

November 2012
Nov. 13, 2012 NanoMEMSSponsored by: IEEE San Francisco Bay Area Nanotechnology CouncilCo-sponsored by IEEE Electron Devices Society SCV Chapter

Time: Tuesday, November 13, 2012 Noon-1PM

 

Speaker: Dr. Héctor J. De Los Santos, NanoMEMS Research, LLC, Irvine, Ca

 

Location:

TI Auditorium E-1, 2900 Semiconductor Drive. Santa Clara
Seminar Program

October 2012
Oct. 25, 2012 Fourth Annual IEEE-SCV Soft Error Rate (SER) WorkshopSponsored by: Cisco Systems, Inc.and the CPMT, Electron Devices, and Reliability chapters of IEEE, Santa Clara Valley

Chair: Peng Su, Ph.D., Component Quality and Technology Group, Cisco Systems, Inc.

 

Program Chairs: Shi-Jie Wen and Rick Wong, Cisco Systems, Inc.
Location:

On the campus of Cisco Systems:

Building 15, First Floor (Sunken Treasures Conference Room), 3750 Cisco Way, San Jose

 

Also broadcast LIVE on the Internet, via WebEx (same registration procedure)

 

Cost: Free; Advance registration required
Workshop Program

Registration

 

IEEE Santa Clara Valley (SCV) Electron Devices Society (EDS) Annual Presentation: General Information & Membership Benefits

Please click here to view the presentation slides.