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Past Events

Webex link will be distributed to the registrant via email.

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Heterogeneous Integration Roadmap Symposium and Annual Meeting [more]
— intro to HIR v1.0, overviews, integration, working groups, 15-year projections …
— Thurs (at Samsung in SJ) & Friday (at SEMI in Milpitas), February 20-21, 2020
— $50 for IEEE/ASME members; $60 for non-members; $25 for retired/students (includes two lunches)

Speakers: from Intel, Boeing, Fraunhofer, NASA, Infineon, Google, Advantest, ASE, ITRI, SEMI, UI-UC, U-Md, UCLA, more
Who should attend: Engineers and managers in the materials, devices, photonics, packaging, supply chain, assembly and test disciplines; Open to the General Public
Summary: Heterogeneous Integration will be the key technology direction going forward, for device and subsystem integration. It is the “low hanging fruit” for initiating a new era of technological and scientific advances. The 2019 HIR edition was released October 2019. This Annual Meeting kicks off the revision work for the 2020 HIR Edition.
Day 1: Progress toward Heterogeneous Integration: Implementation of HIR v1.0; Work on v2.0 — Presentations from all 22 HIR Technical Working Group chairs; panels     — How to Download and Use the Roadmap
Keynote Speakers: Pradeep Dubey, Intel Sr Fellow; Hong Liu, Distinguished Engineer & Senior Director, Google Technical Infrastructure
4 Sessions: — Heterogeneous Integration for High Performance;   — Heterogeneous Integration for Consumer & Industrial Applications;   — Heterogeneous Integration for High-Performance Computing;   — Heterogeneous Integration for Special Applications
Day 2: TWG Breakout Sessions for HIR v2.0     — TWG Caucuses & Cross-TWG meetings
For a full information, please see the website: www.cpmt.org/scv/?p=999

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EDS Distinguished Lecturer Mini-colloquium

We have a mini-colloquium presented in partnership with the IEEE EDS DL Program and the SJSU Electrical Engineering Department.

Friday, December 6, 2019 1PM-3PM – No cost to attend

San Jose State University Charles W. Davidson College of Engineering, Room E285/287

Distinguished Lecturers and Topics

Current progress and future perspectives in polymer solar cells, Lluís F. Marsal, Professor, University of Rovira i Virgili, Spain

Physics and modeling of organic thin film transistors, Benjamin Iñiguez, Professor, University of Rovira i Virgili, Spain

Silicon technologies for 5G, Anirban Bandyopadhyay, Director, GLOBALFOUNDRIES, Inc.

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Current progress and future perspectives in polymer solar cells

Polymer solar cells are considered as a promising renewable energy source because of their
light-weight, high transparency, possibility of fabrication in large areas and inexpensive solar
energy production. These solar cells are based in the junction of two different organic
semiconducting materials, one donor and one acceptor. The most efficient devices to date are
the bulk heterojunction cells, obtained from a mixture of the donor and acceptor materials,
which provides an enormous interfacial surface.
In the last years, advances in polymer-based organic solar cells have been possible due to
different approaches such as design of new structures and synthesis of new materials such as
small molecule and polymers with low band-gaps, control of the nanoscale morphology, new
interfacial transport layers, variation of the ratio of the donor/acceptor in the bulk
heterojunction, application of thermal or solvent annealing process, among others [1-4]. As
a result, recently, power conversion efficiencies over 16% are obtained. However, there are
still some problems to solve such as the stability, more efficient architectures and degradation
process of the polymeric solar cells. In this lecture, we will present the perspectives and
recent advances made in polymer solar cells, design and synthesis of new polymers and in
particular the active layer morphology, interfacial layers and stability. We will also discuss
the basic device operation and various parameters limiting their efficiency and their possible
solutions.

Prof. Lluis F. Marsal is Distinguished Professor and full
professor at the University Rovira i Virgili, Spain. Ph.D. from
the University Politecnica de Cataluña, Spain, 1997.
Postdoctoral researcher at the ECE, University of Waterloo,
Canada (1998-1999).
In 2012, he received the URV’s RQR Award for the high quality
in research and in 2014, he received the UniSA Distinguished
Researcher Award, and the 2014 ICREA Academia Award
from the Generalitat of Catalunya. Since 2019, he is the Chair
of the Subcommittee for Regions/Chapters (SRC) – Regions
8, IEEE- EDS. He was the Chair of Spain Chapter of the IEEE-EDS (2013-2018). He
is a senior member of the IEEE and a member of the Distinguished Lecturer program
of the EDS. He has co-authored more than 200 publications in international refereed
journals, 2 books, 5 book chapters and 3 patents. His current research interests
focus on organic and hybrid solar cells and nanostructured materials for
optoelectronic devices and low–cost technologies based on micro- and nanoporous
materials for biosensing and bio-applications.

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Speaker: Hideki Takeuchi, Atomera Inc.

Tuesday, August 13, 2019 at 6:00PM

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IEEE EDS Distinguished Lecturer Series

Title: Nitrided and Fluorinated Graphene for the Applications on High Mobility Graphene Transistor, Memory and Chemical Sensors

Speaker: Prof. Chao-Sung Lai, Chang Gung University

Thursday, May 30, 2019 at 6:00PM

Abstract

A novel graphene based insulator, fluorographene, is firstly applied as gate dielectric in a field effect transistor. To identify the dielectric quality, dielectric constant, breakdown electric field and thermal stability are investigated. In this talk, the scalable and one-step fabrication of single atomic-layer transistors is demonstrated by the selective fluorination of graphene using a low-damage CF4 plasma treatment, where the generated F-radicals preferentially fluorinated the graphene at low temperature (<200 °C) while defect formation was suppressed by screening out the effect of ion damage. The fluorographe was also used as decoupling for graphene as its substrate and mobility was improved much. Graphene nanodiscs (GNDs), functionalized using NH3 plasma, as charge trapping sites (CTSs) for non-volatile memory applications have been investigated. The fabrication process relies on the patterning of Au nanoparticles (Au-NPs), whose thicknesses are tuned to adjust the GND density and size upon etching. A GND density as high as 8 × 10¹¹ cm⁻² and a diameter of approximately 20 nm are achieved. The functionalization of GNDs by NH3 plasma creates NH⁺ functional groups that act as CTSs, as observed by Raman and Fourier transform infrared spectroscopy. This inherently enhances the density of CTSs in the GNDs, as a result, the charge loss is less than 10% for a 10-year data retention testing, making this low-temperature process suitable for low-cost non-volatile memory applications on flexible substrates. Moreover, the pH, pNa ion sensing properties of graphene based ion-sensor by nickel end contact modification were demonstrated. The pH and pNa sensitivities were around 36.5mV/pH and 15.3mV/pNa, respectively, for pristine graphene. For Ni end-contact modified graphene, sensitivities are changed to 41mV/pH and no pNa sensitivity.

Speaker Biography
Chao-Sung Lai received the B. S. and ph. D. degrees from National Chiao Tung University, Hsinchu, Taiwan, in 1991 and 1996, respectively. In 1996, he joined National Nano Device Laboratories, Hsinchu, where was engaged in the research of silicon-on-insulator devices. He then, in 1997, joined Chang Gung University as a faculty in the department of electronic engineering. He has been engaged in the research of the characterization and reliability of MOSFETs, Flash memory and transistor based biosensors. From 2001 to 2002, he visited the Department of Electrical Engineering, University of California, Berkeley, for visiting research on fin-shaped FETs. Since 2007 to 2013, he had been the Chairman of the Department of Electronic Engineering and the Director of the Biosensor Group of the Biomedical Research Center, Chang Gung University, for the research-related bio-transistor application on ions, proteins, DNA, and biomarker analysis. From 2012 till now, he is the Dean of Engineering College of Chang Gung University. He holds 11 U.S. patents and 60 Taiwan patents, and he is the author of more than 350 SCI journal and conference papers, 25 international invited talks, and 2 book chapters. He is the Leading Guest Editor of the SCI journals, including Microelectronics Reliability (2010), Nano-Scaled Research Letters (2011), and Solid-State Electronics (2012). He won Lam Research Award in 1997 and distinguished award from Electron Devices and Materials Association in 2011 and Association of Chemical Sensing Technology in 2015. From 2016, he was elected as the president of Association of Chemical Sensing Technology. He has served as organizing committees for several international conferences, including general chair (IEEE-INEC 2011), (IEEE-ISNE 2015) and international advisory committee (IEEE-ISNE 2016) and (IEEE-EDSSC 2017).

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Saturday, May 11, 2019 at 10:30AM

Title: Simulations of Nanoscaled Transistors Including Self-Heating Effects: From Coupled Phonon/Carrier Boltzmann Equations Approach to Coupled Drift-Diffusion/Heat Equations Model

Speaker: Dr. Anh-Tuan Pham, Samsung Semiconductor, Inc

Abstract

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April 9, 2019

Using new physics of nonlinear electronics for analog computing

Speaker: Dr. Suhas Kumar, HP Lab

Abstract

There is growing interest for nonlinear electronic behaviors that may enable analog computing such as brain-like neuromorphic computing, which cannot be efficiently achieved using any traditional transistor-based circuits. Nonlinear electronic components, such as memristors and neuristors, which can emulate synapses and neurons, are enabled by device physics that are barely understood. This talk will summarize some new materials physics that have enabled new device behaviors. And the talk will also highlight how the new device behaviors can enable certain analog neural network hardware for NP-hard combinatorial optimization, which cannot be implemented with any practical efficiency using traditional digital electronics.

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March 5, 2019

“Spintronics-Perspectives and Challenges”

Speaker: Prof. Brajesh Kumar Kaushik, IIT

Abstract

Conventional CMOS technology has reached to the brink of its scaling limits and poses significant challenges for the development of next generation high-speed ultra-low power cost-effective memory and processing devices. The failure of Moore’s law on the technology roadmap has enforced the research community to explore alternative technology solutions to mitigate the problems. In the post-CMOS era, spintronics shall emerge as a potentially viable interdisciplinary field with credible technological perspectives. Spintronic exploits an electron’s spin orientation and its associated magnetic moment as a state variable instead of a conventionally used charge in CMOS technology. In general, the spintronic devices are layered structure of ferromagnetic materials and provide the nonvolatile storage options and manipulations of logic states. Spin transfer torque (STT) and spin orbit torque (SOT) devices using magnetic tunnel junctions (MTJs) have become strong contenders for the nonvolatile embedded memory architectures with the capability of implementing the concepts of “logic-in-memory” and “material-device-circuit co-design.” The spin torque devices offer the features of “universal memory” i.e., high speed, nonvolatility, high density, and low power, high endurance, CMOS process compatibility. Apart from the basic spin torque devices, the field of spintronics encloses all spin logic (ASL) devices, domain wall (DW) based devices, spin diodes, and spin FETs. The material and device level roadmaps for the field of spintronics suggest that the research work is at the infant stage and still require different elemental spin device developments with the understanding of associated underlying physics. In addition, the accurate models for the spintronic devices imitating the effect of stochastic behaviour and PVT variations need to be explored. Spintronics based architectures are being considered for computing applications such as bio-inspired computing and quantum computing. These spintronics based novel computing approaches find applications in image processing and provides efficient solution to the complex computing problems.

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January 22, 2019

“Novel Technologies for Artificial Intelligence: Prospects and Challenges”

Speaker: Dr. Stefano Ambrogio, IBM Almaden

Abstract

Recently, Artificial Intelligence (AI), exploiting both bio-inspired algorithms, such as Spike-Timing-Dependent-Plasticity (STDP), or back-propagation algorithms, as in Deep Neural Networks (DNNs), are able to perform accurate classification of large amounts of data. However, to further proceed in the development of AI, novel hardware technologies supporting fast calculation should be developed. Recently, many algorithms have been efficiently mapped into arrays of Non-Volatile Memories, such as Phase-Change Memory (PCM) or Resistive Memory (RRAM) [1,2].

In this presentation, we provide a summary of recent progress in hardware acceleration of AI algorithms, such as the training of Fully Connected (FC) DNNs based on large arrays of PCMs. In such schemes, weights are encoded in the conductances of resistive devices, with orders of magnitude estimated increase in speed and energy efficiency with respect to current state of the art based on CPUs and GPUs [2].

In addition to speed and power consumption, the desired chip for FC DNNs training should also provide equivalent accuracy to software training. We recently provided a novel weight scheme based on PCM and CMOS circuitry able to obtain software-equivalent training accuracy on MNIST and other small and medium size datasets. Results were obtained with a mixed hardware-software experiment where CMOS circuitry was accurately simulated and PCM behavior was measured from real device arrays [3].

After this, we provide some design guidelines for the implementation of a multicore chip able to perform training of DNNs. This is obtained with many NVM arrays connected through a routing circuitry able to efficiently distribute internal signals, external inputs such as images and labels and, finally, providing the trained weights to the output [4].

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December 1, 2018

“Improving the IEEE: Issues, Ideas, Best Practices”

Moderator: Dr. Renuka Jindal, Director, IEEE Division I

Abstract

This will be an event “for listening to” engineers and managers in Silicon Valley who have ideas for improving the IEEE, or have issues they’d like to raise. With input and grass-roots suggestions for improving the IEEE, I intend to provide actionable feedback at the IEEE TAB and BOD level. Your input will be critical in shaping the future of the IEEE and will need your active support to make this a reality.
If you wish to bring specific thoughts about IEEE changes, improvements and growth, be prepared to present them to the group for, say, 5 minutes, for discussion and enhancement. The meeting secretary will take notes, along with any handouts you provide, and ask for others who would like to be further involved with your specific suggestion. Renuka will receive your inputs and the summary, and is taking steps to allow him to gather world-wide input on these specific ideas that can inform and support the issues that are raised by our SV community of entrepreneurs.

Speaker Biography

Dr. Renuka Jindal’s technical focus has been on research and teaching in the theory and practice of random processes applicable to a wide variety of phenomena in electronic and photonic devices and circuits, lightwave and wireless communications and biological systems. He was with Bell Labs at Murray Hill, Princeton and Whippany, NJ as a distinguished member of technical staff for 22 years, bridging both technical and administrative roles. Highlights include his pioneering work in developing a physical understanding of noise in MOS devices with few hundred nanometers regime channel lengths and ultra-low noise amplification of fiber-optic signals. Until recently, he has served as Professor of Electrical and Computer Engineering, University of Louisiana at Lafayette.
As a 41 year veteran of IEEE with a dual career in industry and academia, Dr. Jindal rose through the ranks as Editor, Editor-in-Chief, VP of Publications, and as EDS president in 2010-2011, and now serves as Director of IEEE Division I, sitting on the IEEE Board. As EDS president he formulated the vision and mission of EDS, enhancing member benefits and launching a plethora of initiatives reversing the decline in EDS membership. He brought together 6 societies and 1 council to launch the highly successful IEEE Journal of Photovoltaics, mushrooming IEEE’s share in the PV space. He Launched the EDS webinar series serving the practicing engineer, now considered a best practice in IEEE. And he Launched the 1st EDS OPEN ACCESS Journal J-EDS. He is also a recipient of the IEEE 3rd Millennium medal.

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November 30, 2018

“Materials, Devices, and Modeling of Advanced Semiconductor Devices – An IEEE EDS Distinguished Lecturer Double-Header”

Moderator: Dr. Renuka Jindal, Director, IEEE Division I

Talk 1: Are Extended Defects a Show Stopper for Future III-V CMOS Technologies, Cor Claeys, KU Leuven

The progress in epitaxial growth techniques resulted in intensive research on the potential use of non-Si based substrates, enabling the fabrication of Ge (p-channel), III-V (n-channel) or hybrid Ge/III-V devices on a Si substrate. These high mobility materials are also implemented in TFET and nanowire structures. Heterogenous integration of Ge and III-V technologies on a silicon platform enables to fabricate System-on-Chip applications and has potential for Internet-of-Things (IoT) applications. The aspect-ratio-trapping (ART) heteroepitaxy technique is successfully applied for the fabrication of non-planar devices like for Gate-All Around structures, FinFETs and TFETs. Due to the lattice mismatch between Si and the device layer (Ge or III-V), the challenge is to suppress or minimize the formation of
misfit and threading dislocations.

First a review is given of some of the present-day state-of-the art III-V devices processed on a Si platform reported in the literature, before addressing defect engineering aspects for III-V processing on a Si-platform from both a structural and electrical performance perspective. The identification of the extended defects will be illustrated by some case studies based on Deep Level transient Spectroscopy (DLTS) analysis and low frequency noise spectroscopy. Information on the basic defect parameters can be used as input for TCAD simulation of the electrical device performance, enabling a further optimization of the materials’ growth and
process conditions. The optimal goal is to determine for real devices the tolerable defect levels without penalizing their performance.

Cor Claeys is Professor at the KU Leuven (Belgium) since 1990. He was with imec, Leuven, Belgium from 1984 till 2016. His main interests are semiconductor technology, device physics, low frequency noise phenomena, radiation effects and defect engineering. He co-edited books on “Low Temperature Electronics” and “Germanium-Based Technologies: From Materials to Devices” and wrote monographs on “Radiation Effects in Advanced Semiconductor Materials and Devices”, “Fundamental and Technological Aspects of Extended Defects in Germanium” and “Random Telegraph Signals in Semiconductor Devices” and “Metals in Silicon- and Germanium-Based Technologies: Origin, Characterization, Control and Electrical Impact”. Two books are translated in Chinese. He (co)authored 14 book chapters, over 1100 conference presentations and more than 1300 technical papers. He is editor/co-editor of 60 Conference Proceedings. Prof. Claeys is a Fellow of the Electrochemical Society and of IEEE. He was Founder of the IEEE Electron Devices Benelux Chapter, Chair of the IEEE Benelux Section, elected Board of Governors Member and EDS Vice President for Chapters and Regions. He was EDS President in 2008-2009 and Division Director on the IEEE Board of Directors in 2012-2013. He is a recipient of the IEEE Third Millennium Medal and received the IEEE EDS Distinguished Service Award. Within the Electrochemical Society, he was Chair of the Electronics &amp; Photonics Division (2001-2003) . In 2004, he received the Electronics &amp; Photonics Division Award. In 2016 he received the Semi China Special Recognition Award for outstanding involvement in the China Semiconductor Technology International Conference (CSTIC).

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Talk 2: Modeling and Simulation of FinFET and Nanosheet Transistors for Advanced Technology Nodes, Yogesh Chauhan, IIT Kanpur

 

Continued scaling of transistors has forced us to scale the channel thickness of the device to have strong electrostatic control and get rid of the short channel effects. The reduced channel thickness results in the confinement of charge carriers and larger quantization effect. In addition to the scaling, alternative channel materials having better transport properties are also being explored to boost the device performance. The promising options for channel materials in post Si era are Ge, SiGe, III-V and 2D layered semiconductors. The III-V semiconductor materials have lower effective mass and as a consequence lower density of states (DOS). The lower DOS introduces a new capacitance component in gate capacitance in addition to the existing charge centroid and gate oxide capacitance and is called as quantum capacitance. Scaling has also resulted in channel lengths of modern and upcoming devices to be comparable to the mean scattering lengths of the semiconductor material. This causes some of the charge carriers to travel from the source to the drain without any significant scattering. Therefore, the generic principles governing the drift-diffusive framework, i.e. (i) the concept of mobility, and (ii) local field dependent velocity, are no longer valid. This quasi-ballistic transport results in significant deviation from the device behaviour predicted by traditional drift diffusive models. Since different carriers experience different amounts of scattering, modeling such devices is not only interesting but also challenging. In this talk, I will discuss the physics and modelling of different quantum effects and transport in extremely scaled transistors with different channel materials.

Yogesh Singh Chauhan is an associate professor at Indian Institute of Technology Kanpur (IITK), India. He was with Semiconductor Research &amp; Development
Center at IBM Bangalore during 2007 – 2010; Tokyo Institute of Technology in 2010; University of California Berkeley during 2010-2012; and ST Microelectronics during 2003-2004. He is the developer of industry standard BSIM-BULK (formerly BSIM6) model for bulk MOSFETs and ASM-HEMT model for GaN HEMTs. His group is also involved in developing compact models for FinFET, Nanosheet/Gate-All-Around FET, FDSOI transistors, Negative Capacitance FETs and 2D FETs.
He is the Editor of IEEE Transactions on Electron Devices and Distinguished Lecturer of the IEEE Electron Devices Society. He is the member of IEEE-EDS Compact Modeling Committee and fellow of Indian National Young Academy of Science (INYAS). He is the founding chairperson of IEEE Electron Devices Society U.P. chapter and Vice-chairperson of IEEE U.P. section. He has published more than 200 papers in international journals and conferences. He received Ramanujan fellowship in 2012, IBM faculty award in 2013 and P. K. Kelkar fellowship in 2015, CNR Rao faculty award and Humboldt fellowship in 2018. His research interests are characterization, modeling, and simulation of semiconductor devices. He has served in the technical program committees of IEDM, SISPAD, ESSDERC, EDTM, and VLSI Design conferences.

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October 9, 2018

“Connecting Atomic Level Material Analysis to Transistor Scale Modeling for FinFET and Nanowire Design”

Speaker: Dr. Victor Moroz, Fellow, Synopsys

Abstract

At 5nm design rules, atomic scale effects kick in on several levels: the bandstructures of Si and SiGe fins deviate from bulk properties, impacting transistor performance by about 10%. Further scaling makes transistor behavior even more sensitive to atomic scale changes in critical layer thicknesses, including fin/nanowire thickness changes as the current flows from source to channel and from channel to drain. We also explore different types of surface roughness due to plasma etch and lithography line edge roughness and its impact on transistor behavior. Quantum transport analysis suggests very non-intuitive engineering of surface roughness that can be transparent to the current flow for certain surface roughness patterns. The emerging role of atomic scale and quantum transport effects indicate a paradigm shift towards bandstructure driven transistor design. A key side effect of this is that the choice between different transistor architectures will come down to imperfections of different architectures and how these imperfections can be controlled and mitigated in high volume manufacturing environment. Atomic scale effects are inherently difficult to capture and quantify experimentally. Therefore, we use rigorous ab-initio physical approach to characterize such effects and extract guidelines for the future transistor design.

Speaker Biography

Victor Moroz received Ph.D. degree in Applied Physics from the University of Nizhny Novgorod in 1992 and joined a Stanford spin-off Technology Modeling Associates in 1995, which later became a part of Synopsys, connecting a design company to the manufacturing.
Currently Dr. Moroz is a Synopsys Fellow and Editor of Electron Device Letters, engaged in a variety of projects on analysis of advanced CMOS technology. Several facets of this activity are reflected in 100+ publications and 100+ granted and pending US patents.

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September 11, 2018

“Mapping emerging memory devices to various applications: SCM, machine learning, in-memory computing, and other”

Speaker: Chris Petti, Fellow, Western Digital Corp.

Abstract

Over the years, there have been many technological candidates for a so-called “universal memory” – something that could replace NAND-FLASH, NOR-FLASH, SRAM, DRAM, etc. These technologies include many different types of resistive memory – oxide-based, conductive bridge, correlated electron, magnetic RAM, etc. Lately, it has become clear that none of these technologies is adequate for all of the usual Von-Neumann-based applications: storage (both “cold” or “hot”), main memory, cache, and other registers. Moreover, other, non-Von-Neumann based applications, including neural networks and in-memory computing, are being developed. The objective of this talk is to create a map of the different types of memory cell technologies to different applications and architectures, and to discuss the device and technology parameters that are most important for this classification.

Speaker Biography

Christopher Petti is an Engineering Fellow and Senior Director of Advanced Technology Development at Western Digital. He came to Western Digital as part of the acquisition of SanDisk in 2016. Dr. Petti has over 25 years of experience in a variety of semiconductor industries, including non-volatile memory, logic and SRAM technologies, flat-panel displays, and solar cells. In these fields, he has specialized in device physics, process integration, product architecture, and product engineering. Dr. Petti holds a B.S. in Physics from the Massachusetts Institute of Technology, and an M.S. and Ph.D. in Electrical Engineering from Stanford University. He is inventor or co-inventor on over 115 issued U.S. patents.

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July 10, 2018

“Predicting Soft Errors and Hard Effects on ICs in Three Radiation Environments (On-the-Ground, In-Airplanes, and In-Space) Based on Accelerated, Accelerator Tests”

Speaker: Gary Swift, Swift Engineering and Radiation Services, LLC

Speaker Biography

Gary M. Swift received a B.S. in Engineering Physics from the University of Oklahoma in 1975 followed by graduate work in Nuclear Engineering at the University of Illinois at Urbana-Champaign. He tested electronic parts for radiation effects for almost two decades at NASA’s Jet Propulsion Laboratory in Pasadena -retiring as a principal engineer- and then for seven years at Xilinx, Inc. Currently, Gary is the Principal Engineer at the independent consulting firm Swift Engineering and Radiation Services, LLC which he founded. SwiftERS specializes in best-practice SEE testing of complex ICs such as FPGAs and microprocessors. He is an influential member of the radiation effects and testing community and has publications on a broad range of radiation effects testing including some on total dose and displacement damage, but most on single-event effects. For example, in 1992, he coined the now widely used term SEFI. Two papers he co-authored were given that year’s NSREC Outstanding Paper Award (1999 and 2015). In 2001, Gary co-founded the Xilinx Radiation Test Consortium, a voluntary group of national labs, universities and aerospace companies that collaborate on SEE testing; since then, he has served as XRTC test coordinator and weekly telecom moderator to the present day.

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Special Event: IEEE EDS @ SJSU Technology Showcase

Saturday, May 19 , 2018

SJSU Student Union
211 S 9th St, San Jose, CA 95112

Free parking (code given by attendant) at SJSU North Parking Garage, 437 E San Fernando St. San Jose, CA 95112

Cost to attend: FREE

Agenda
8:30 ‐ 9:30: Free Continental Breakfast
9:00 ‐ 10:30: IEEE EDS Talk: “Emerging Interconnect Technologies for Nanoelectronics” by Prof. Krishna Saraswat, Department of Electrical Engineering, Stanford University
10:30 ‐ 12:30: SJSU Technology Showcase student project poster presentations
12:30 ‐ 2:30: Free Lunch/Panel Discussion

EDS Talk Abstract

Modern electronics has advanced at a tremendous pace over the course of the last half century primarily due to enhanced performance of MOS transistors due to dimension scaling, introduction of new materials and novel device structures. However, while this has enhanced the transistor performance, the opposite is true for the copper interconnects that link these transistors. Looking into the future the relentless scaling paradigm is threatened by the limits of copper/low-k interconnects, including excessive power dissipation, insufficient communication bandwidth, and signal latency for both off-chip and on- chip applications. Many of these obstacles stem from the physical limitations of copper/low-k electrical wires, namely the increase in copper resistivity, as wire dimensions and grain size become comparable to the bulk mean free path of electrons in copper and the dielectric capacitance. Thus, it is imperative to examine alternate interconnect schemes and explore possible advantages of novel potential candidates. This talk will address effects of scaling on the performance of Cu/low-k interconnects, alternate interconnect schemes: carbon nanotubes (CNT), graphene, optical interconnect, three-dimensional (3-D) integration and heterogeneous integration of these technologies on the silicon platform. Performance comparison of these technologies with Cu/low-k interconnects will be discussed. Prof. Saraswat is the is Rickey/Nielsen Chair Professor of Electrical Engineering at Stanford University.

SJSU Technology Showcase – student project topic areas
• Data Science (Data Mining/Machine Learning/Deep Learning)
• Smart City Apps and Technologies
• Blockchain
• Internet of Thing
• Embedded Systems/Robotics
• Enterprise App Development
• Cloud/Virtualization
• Cybersecurity
• Virtual and Augmented Reality
• ASIC/VLSI/Analog/Mixed-Signal Circuits
• Signal Processing
• Wireless Communications
• Smart Grid/Power Electronics/Control
• Electric Vehicles

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April 16, 2018:

“The Smaller the Better: A Sub-Millimeter Wireless Neural Stimulator”

Abstract:

Wireless neural stimulators are being developed to address problems associated with traditional lead-based implants. However, designing wireless stimulators on the sub-millimeter scale (<1 mm3) is challenging. As device size shrinks, it becomes difficult to deliver sufficient wireless power to operate the device. To address this problem, we have developed a sub-millimeter, inductively powered neural stimulator consisting only of a coil to receive power, a capacitor to tune the resonant frequency of the receiver, and a diode to rectify the radio-frequency signal to produce neural excitation. By replacing any complex receiver circuitry with a simple rectifier, we have reduced the required voltage levels that are needed to operate the device from 0.5-1 V (e.g. for CMOS) to ∼0.25–0.5 V. This reduced voltage allows the use of smaller receive antennas for power, resulting in a device volume of 0.3–0.5 mm3. We have demonstrated the basic proof-of-concept with stimulation of both deep brain and peripheral nerve targets.

Biography:

Daniel Freeman is a Principal Member of the Technical Staff at Draper Laboratory in Cambridge, MA. He received his PhD in Biomedical Engineering from Boston University in 2008 where he investigated light adaptation mechanisms of the retina. This was followed by postdoctoral fellowships at MIT and Harvard Medical School in the area of retinal implants, where he developed methods to selectively excite individual types of neurons. At Draper, Dan has is been involved in a number of programs, including a sub-millimeter neural stimulator, a MEMS electrical field sensor, a mechanical antenna, and a microfluidic electroporation system. Dan currently runs a program on diamond vacuum transistors for rad-hard and low-noise electronics.

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Nano-Material Engineered Interconnect Technologies for Heterogeneous System Integration

Mansun Chan

Dept. of ECE, Hong Kong University of Science & Technology,

Clear Water Bay, Kowloon, Hong Kong

E-mail: mchan@ust.hk

Abstract: The scaling of CMOS has encountered many hurdles in the sub-10nm technology nodes as we are approaching the end of the Moore’s Law. The performance limitations have shifted to the interconnect technology to reduce the metal wire resistance as well as the k-value of the interlayer dielectrics. The popular interconnect materials such as copper and tungsten have been found to be insufficient due to increasing resistivity with dimension scaling and electromigration concern under high current density. And using porous structures to form the interlayer dielectrics is subjected to the weakening of the mechanical strength of the dielectric film. New materials such as carbon nanotube (CNT) and graphene have been extensively studied to extend the scaling roadmap for interconnects. However, many barriers have to be overcome before these materials can enter mainstream manufacturing. In this presentation, I am going to present some of the recent progresses in using CNT as a contact plug as well as an agent to form very low k-value interlayer dielectrics.

Biography:

Prof. Mansun Chan received his BS in Electrical Engineering and Compute Science with highest honors from the University of California at San Diego and then completed his MS and PhD at the University of California at Berkeley. At Berkeley, was one of the major contributors to the unified BSIM model for SPICE, which has been accepted by most US companies and the Compact Model Council (CMC) as the first industrial standard MOSFET model. Subsequently, he joined the Electrical and Electronic Engineering Department at Hong Kong University of Science and Technology. His research interests include emerging nano-device technologies, 2-D device for flexible electronics, Artificial Neural Network devices and applications, new-generation memory technology, BioNEMS, device modeling and ultra-low power circuit techniques. Between July 2001 and December 2002, he was a Visiting Professor at University of California at Berkeley and the Co-director of the BSIM program. He is currently still consulting on the development of the next generation compact models.

Prof. Chan has been actively contributing to the professional community and hold many positions. He is a Board of Governor, Chair of the Education Committee, the Chair of the Region 10 subcommittee and a Distinguished lecturer of the IEEE Electron Device Society. He has also chaired many international conferences and acting as editors for a number of technical journals. In addition, he has received many awards including the UC Regents Fellowship, Golden Keys Scholarship for Academic Excellence, SRC Inventor Recognition Award, Rockwell Research Fellowship, R&D 100 award (for the BSIM3v3 project), Distinguished Teaching Award, the Shenzhen Science and Technology Innovation awards etc. He is a Fellow of HKIE, IET and IEEE.

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December 8:

IEEE SCV-SF Electron Devices Society Seminar “2D Electronics — Opportunities and Challenges”

Prof. Frank Schwierz, TU Ilmenau

An IEEE-EDS Distinguished Lecture

Location: Packard Building 101, Stanford University

Date: Friday December 8, 4:00 PM

Parking information: 

https://transportation.stanford.edu/parking/about-parking-permits/view-parking-and-circulation-map

Visitors should park in the Via Ortega Garage, the Roble Field Garage, or the Roth Way Garage (in that order of preference) and parking is FREE after 4pm. (This is one of the reasons for having the seminar at that time.)

Abstract: During the past decade, 2D (two-dimensional) materials have attracted enormous attention from various scientific communities ranging from chemists and physicists to material scientists and device engineers. The rise of the 2D materials began in 2004 with the work on graphene done at Manchester University and Georgia Tech. Particularly the observed high carrier mobilities raised early expectations that graphene could be a perfect electronic material. It soon became clear, however, that due its zero bandgap graphene is not suitable for most electronic devices, in particular transistors. On the other hand, researchers have extended their work to 2D materials beyond graphene and the number of 2D materials under investigation is continuously rising. Many of them possess sizeable bandgaps and therefore are considered to be useful for transistors. Indeed, the progress in the field of 2D transistors has been rapid and experimental MOSFETs using semiconducting 2D channel materials have been reported by many groups. A recent achievement was the demonstration of a well-performing 1-nm gate MoS2 MOSFET in 2016. On the other hand, and in spite of the progress in the field, the debate on the real prospects of the 2D materials for future electronics is still controversial.

In the present lecture, the most important classes of 2D materials are introduced and the potential of 2D transistors is assessed as realistically as possible. To this end, two material properties – bandgap and mobility – are examined in detail and the mobility-bandgap tradeoff is discussed. The state of the art of 2D transistors is reviewed by summarizing relevant results of leading groups in the field, presenting examples of the lecturer’s own work on 2D electronics, and comparing the performance of 2D transistors to that of competing conventional transistors. Based on these considerations, a balanced view of both the pros and cons of 2D transistors is provided and their potential in both the More Moore (digital CMOS) and the More Than Moore domains of semiconductor electronics is discussed. It is shown that due to the rather conservative CMOS scaling scenario of the 2015 ITRS (compared to the more aggressive scenarios of the previous ITRS editions) it will be difficult for 2D materials to make inroads into mainstream CMOS. However, due to their specific properties (for example, 2D materials are bendable and stretchable) they may enable entirely new applications in the More Than Moore domain.

 

Bio: Frank Schwierz received the Dr.-Ing. and Dr. habil. degrees from Technische Universität (TU) Ilmenau, Germany, in 1986 and 2003, respectively. Presently he serves as Privatdozent at TU Ilmenau and is Head of the RF & Nano Device Research Group. His research interests include semiconductor device physics, novel device and material concepts for future transistor generations, and high-performance radio frequency transistors. At present he is particularly interested in two-dimensional electronic materials.

Dr. Schwierz is conducting research projects funded by the European Community, German government agencies, and the industry. Together with partners from academia and industry he was involved in the development of the fastest Si-based transistors worldwide in the late 1990s, of Europe’s smallest MOSFETs in the early 2000s, as well as of the fastestGaN HEMTs on Si and the fastest GaN tri-gate HEMTs worldwide in the 2010s. His recent work on two-dimensional materials made a major contribution to the current understanding of the merits and drawbacks of graphene transistors.

Dr. Schwierz has published more than 260 journal and conference papers including 40 invited papers. He is author of the books Modern Microwave Transistors – Theory, Design, and Performance (J. Wiley & Sons 2003) and Nanometer CMOS (Pan Stanford Publishing 2010) and editor of the book Two-Dimensional Electronics – Prospects and Challenges (MDPI 2016).

Dr. Schwierz is Senior Member of the IEEE. He serves as a Distinguished Lecturer of the IEEE Electron Devices Society and as an editor of the IEEE Transactions on Electron Devices. Moreover, he is one of the key contributors to the Emerging Research Devices Technology Working Groups of the 2013 and 2015 ITRS editions.

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December 6:

Time: December 6, 2017

Location: Cadence Office; Silicon Valley

Synopsis: The MOS-AK Association is organizing 10th successive compact modeling workshop in the timeframe of the IEDM and CMC Meetings on Dec.6, 2017 in Silicon Valley. The MOS-AK workshops are open HiTech forums to discuss the frontiers of electron device modeling with emphasis on simulation-aware models. MOS-AK Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and its Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all the important aspects of compact model development, implementation, deployment and standardization within the main theme – frontiers of the compact modeling for nm-scale MEMS designs and CMOS/SOI circuit simulations.

Topics: to be covered include the following:
• Advances in semiconductor technologies and processing
• Compact Modeling (CM) of the electron devices
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• FOSS TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, TFT CMOS and SOI-based memory cells
• Organic, Bio/Med devices/technology modeling
• Microwave, RF device modeling, HV/Power device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and IC Designs
• Foundry/Fabless Interface Strategies

Online registration:
http://www.mos-ak.org/silicon_valley_2017

FOSS TCAD/EDA tools for advanced nano-device modeling
Wladek Grabinski
MOS-AK (EU)

Abstract:
Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes; thru the MOSFET, FDSOI, FinFET and TFET compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present two FOSS CAD simulation and design tools: ngspice and Qucs. Application and use of these tools for advanced IC design (e.g. analog/RF IC applications) directly depends the quality of the compact models implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the transistor level and then trigger further discussion on the compact/SPICE model Verilog-A standardization and development supporting FOSS CAD tools.

Biography:
Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, Poland, in 1991. From 1991 to 1998 he was a Research Assistant at the Integrated Systems Lab, ETHZ, Switzerland, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPFL, and was engaged in the compact MOSFET model developments supporting numerical device simulation and parameter extraction. Later, he was a technical staff engineer at Motorola, and subsequently at Freescale Semiconductor, Geneva Modeling Center, Switzerland. He is now an consultant responsible for modeling, characterization and parameter extraction of MOST devices for the IC design. He is currently consulting on the development of next-generation compact models for the nanoscaled technology very large scale integration (VLSI) circuit simulation. His current research interests are in high frequency characterization, compact modeling and its Verilog-A standardization as well as device numerical simulations of MOSFETs for analog/RF low power IC applications. He is an editor of the reference modeling book Transistor Level Modeling for Analog/RF IC Design and also authored or coauthored more than 50 papers. Wladek is the chair of the ESSDERC Track4: “Device and circuit compact modeling” as well as has served as a member of organization committee of ESSDERC/ESSDERC, TPC of SBMicro, SISPAD, MIXDES Conferences; reviewer of the IEEE TED, IEEE MWCL, IJNM, MEE, MEJ. He is a Member At Large of Swiss IEEE ExCom and also supports the EPFL IEEE Student Branch acting as its Interim Branch Mentor. Wladek is involved in activities of the MOS-AK Association and serves as a coordinating manager since 1999.

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November:

IEEE SCV-SF Electron Devices Society Seminar “From Molecules to Pavlov’s Dog: Using Conjugated Polymers to Make Artificial Synapses”

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October:

IEEE SCV-SF Electron Devices Society Seminar “Reliability challenges for the qualification of Leading Edge CMOS Technologies”

Abstract:
This presentation will address some of the key reliability challenges during the qualification of leading edge CMOS technologies. Some of the issues are driven by self heating in SOI and some by the latest trends in semiconductor fabrication as we continue to scale and deal with the new reliability challenges introduced by the use of High K Metal Gate (HKMG) and FinFet devices. We will discuss the reliability impact and the qualification activities driven by the introduction of SOI and new materials. The path to maintaining the advanced CMOS scaling cadence and new reliability limiting factors will be examined from the reliability perspective. A closer look will be given to Hot Carriers, Bias Temperature Instabilities and Gate Dielectric Integrity. The characterization, models and qualification methodologies will be put in the required perspective for the successful qualification and transfer of leading edge technologies to a manufacturing environment.

Biography:
Dr. Fernando Guarín is a Distinguished Member of Technical Staff at Global Foundries in East Fishkill NY. He retired from IBM’s Semiconductor Research Development Center after 27 years as Senior Member of Technical Staff. He earned his BSEE from the “Pontificia Universidad Javeriana”, in Bogotá, Colombia, the M.S.E.E. degree from the University of Arizona, and the Ph.D. in Electrical Engineering from Columbia University, NY He has been actively working in microelectronic reliability for over 35 years. From 1980 until 1988 he worked in the Military and Aerospace Operations division of National Semiconductor Corporation. In 1988 he joined IBM’s microelectronics division where he worked in the reliability physics and modeling of Advanced Bipolar, CMOS and Silicon Germanium BiCMOS technologies. Dr. Guarín is an IEEE Fellow, Distinguished Lecturer for the IEEE Electron Device Society, where he has served in many capacities including; member of the IEEE’s EDS Board of governors, chair of the EDS Education Committee, Secretary for EDS. He is the EDS President-Elect 2016-2017.

Aug 8th, 2017

Recent Progress in Memory Technology ReliabilitySpeaker: Dr. Bob Gleixner, Micron Technology Inc.Link to slides

July 11th, 2017

System Level ESD: A New FocusSpeaker: Dr. Charvaka Duvvury, ESD ConsultingLink to slides

June 13th, 2017

Device and Process VariabilitySpeaker: Dr. Tomasz Brozek, Technical Fellow and Engagement Director at PDF Solutions, San Jose, CALink to slides

May 9th, 2017

New Visions for IC Yield Detractor DetectionSpeaker: Bill Nehrer, VP and Account General Manager, PDF Solutions, San Jose, CA

March 14th, 2017

Progress Toward Wafer-Scale Thermionic Energy ConvertersSpeaker: Prof. Roger Howe, Dept. of Electrical Engineering, Stanford Nano Fabrication Facility, Stanford University

2016 Past Events

Dec 1st, 2016

On-Chip ESD Protection Design: Yesterday, Today, Tomorrow and FutureSpeaker: Prof. Albert Wang, University of California, Riverside

Nov 11th, 2016

IEEE SCV-SF EDS Annual Symposium Device Circuit Interaction in Advanced Technology Nodes

Oct 11th, 2016

Time-Zero and Time-Dependent Variability in Advanced CMOSSpeaker: Dr. Jeffrey T. Watt, Intel Fellow, Intel Corp. Lecture slides

Sept 30th, 2016

Mini-colloquium Emerging Devices, Materials and Technologies Speaker(s): Leading scientists and engineers, including EDS Distinguished Lecturers

Aug 9th, 2016

Circuit Device Interactions and co-optimizations, from system and chip design to process integration – The secret sauce for complex SOC chips and SIPs in advanced technology nodesSpeaker: Dr. John Hu, Director of Advanced Technology, Nvidia Corp., Santa Clara, CA

July 12th, 2016

Electronics and Energy Applications of 1D and 2D NanomaterialsSpeaker: Dr. Eric Pop, Associate Professor of Electrical Engineering , Stanford University, Stanford CALecture slides

May 10th, 2016

Designing with FinFETsSpeaker: Dr. Witold (Witek) P. Maszara, GLOBALFOUNDRIES, Santa Clara, CA

June 14th, 2016

High Frequency Characterization of TransistorsSpeaker: Dr. Jayasimha Prasad, Device/Process Integration Engineer, Foveon Inc, San Jose CALecture slides

Apr. 12th, 2016

Learnings and insights from 52 years of Silicon Valley semiconductor experienceSpeaker: Ray Zinn, Founder and CEO of Micrel, San Jose, CAVideo recording of presentation

Mar. 8, 2016

Technology CAD from Electronics to BioelectronicsSpeaker: Dr. Yang Liu, Professor at the College of Information Science and Electronic Engineering, Zhejiang University, China

Feb. 9, 2016

Everything You Wish to Know about Memristors But Are Afraid to Ask Speaker: Dr. Leon Chua, Professor of EECS, University of California, BerkeleyLecture links

2015 Past Events

May. 19, 2015

Nanoscale Vacuum ElectronicsSpeaker: Dr. Meyya Meyyappan, Chief Scientist for Exploration Technology at NASA Ames Research Center in Moffett Field, CA

Feb. 10, 2015

A photovoltaic diode array as a retinal prosthesis for patients with degenerative retinal diseasesSpeaker: Dr.Theodore I. (Ted) Kamins, Stanford University   IEEE SCV Electron Devices SocietyIEEE Photonics Society co-sponsoredAbstract/bio  Slides

2014 Past Events

August 12, 2014

Graphene and Beyond-Graphene 2D Crystals for Next-Generation Green ElectronicsSpeaker: Dr. Kaustav Banerjee, University of California, Santa BarbaraIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio  Directions

July 29, 2014

Mesoscopic Devices and Their Impact on Product Yield: The Next Technological Challenge  Speaker: Dr. Renuka P. Jindal, Fellow, IEEE, University of Louisiana at Lafayette, LA, USA  IEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio  Directions

June 10, 2014

Parallel Revolutions: How Breakthroughs in Electronics and Biology are Converging at the Molecular ScaleSpeaker: Dr. Jim Hollenhorst, Agilent TechnologiesIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio  Slides (with video link)

April 15, 2014

System Level On-Chip ESD ProtectionSpeaker: Dr. Vladislav Vashchenko, Maxim Integrated CorpIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio  Slides

March 11, 2014	The Roadmap to Success: 2013 ITRS UpdateSpeaker: Dr. Paolo Gargini, Chairman of ITRS and IEEE/IEC/Intel FellowIEEE SCV Electron Devices SocietyCo-sponsored by SF Bay Area Nanotechnology Council Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio  Slides
March 5, 2014	Bionic Skins with Ulraflexible Organic DevicesSpeaker: Takao Someya, School of Engineering, The University of Tokyo, 3-7-1 Hongo, Bunkyo-ku, Tokyo, JapanStanford University and IEEE SCV Electron Devices Society Location: the Allen Building room 101X, Stanford UniversityTime: 4:15pm Abstract/bio

Feb 18, 2014

Product Level Reliability Challenges Originating from TDDB, BTI and VariabilitySpeaker: Dr. Tanya Nigam, GlobalFoundriesIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio  Directions

November 2013

Nov 19, 2013

Eastern Europe’s Semiconductor Technology – Recollections and Projections Speaker: Dr. C. BuluceaIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio  Slides

October 2013

Oct 8, 2013

How far can we push Si CMOS and what are the alternatives for future ULSI Speaker: Prof. K. Saraswat, Stanford UniversityIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio  Slides

September 2013

Sept 24, 2013

Low Power Circuit Design Techniques for Nano-Scale Era Speaker: Dr. R. V. Joshi, IBMIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio

September 2013

Sept 6, 2013

Annual SymposiumPower Electronics: Beyond the Silicon LimitAbstract: Power electronics is re-emerging as an important and innovative area. This is due to the increasing importance of electricity in our lives, and the need to use it more efficiently. … (click to read more) Speakers:Deva Pattanayak (Senior Director at Vishay Siliconix)Alex Lidow (CEO of EPC)Dave Anderson (Chief Technologist and General Manager of Texas Instruments Kilby Labs Silicon Valley)Johan Strydom (Head of Applications Engineering at EPC)Don Disney (Sr. Director of Technology and Product Development atAvogy)Abstracts/bio

July 2013

Jul 9, 2013

Memristive Devices for Computing Speaker: Dr. J. Joshua Yang, Hewlett Packard LaboratoriesIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio

June 2013

Jun 11, 2013

A Complete NBTI DC / AC Model for SiON and HKMG p-MOSFETs Speaker: Prof. Souvik Mahapatra, Indian Institute of Technology Bombay, MumbaiIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio

April 2013

Apr 9, 2013

High-Efficiency, Flexible, Thin-Film, III-V Solar Cells Speaker: Dr. Brendan Kayes, Alta DevicesIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio

March 2013

Mar 12, 2013

Electronics Applications of Carbon Nanotube and Graphene Speaker: Prof. H.-S. Philip Wong, Stanford UniversityIEEE SCV Electron Devices Society, co-sponsored by IEEE SFBA Nanotechnology Council Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio

February 2013

Feb 12, 2013

Towards Storage Class Memory: 3-D crosspoint access devices using Mixed-Ionic-Electronic-Conduction (MIEC) Speaker: Dr. Geoffrey W. Burr, IBM Almaden Research CenterIEEE SCV Electron Devices Society, co-sponsored by IEEE SFBA Nanotechnology Council Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Abstract/bio Slides

November 2012

November 13, 2012

Analog Technologies: Status & Opportunities Speaker: Dr. Albert Bergemont, Vice President of Technology, Research & Development, Maxim Integrated Products.IEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Abstract/bio

October 2012

October 9, 2012

Device Considerations for Low Power VLSI Circuits Speaker: Dr. Robert Rogenmoser, Senior Vice President, Product Development and Engineering, SuVolta, Inc.IEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Abstract/bioPresentation Slides

August 2012

August 14, 2012

Nanoscale CMOS Contacts: Science and Technology Speaker: Dr. Khaled Ahmed, Applied MaterialsIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Abstract/bio

June 2012

June 18, 2012

A Unified Compact Model for Generic Heterostructure HEMTs Speaker: Dr. Xing Zhou, School of Electrical & Electronic EngineeringNanyang Technological University, SingaporeIEEE SCV Electron Devices Society Distinguished Lecture Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Abstract/bioPresentation Slides

May 2012

May 8, 2012

Next Generation Photovoltaics Speaker: Prof. Sue A. Carter, Physics Department, University of California, Santa CruzIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052. Abstract/bio

April 2012

April. 10, 2012

2D Carbon/Semiconductor-Enabled Electronics Speaker: Prof. Bin Yu, College of Nanoscale Science & Engineering, State University of New York – AlbanyIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052. Abstract/bioPresentation Slides

March 2012

Mar. 20, 2012

FinFET/Trigate FET and Its SPICE Model Speaker: Professor Chenming Hu, EECS, UC Berkeley, CA, USAIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Abstract/bioPresentation Slides

February 2012

Feb. 15, 2012

2011 International Technology Roadmap for Semiconductors (ITRS) Update – Overview and Highlights Speaker: Alan K. Allan, Intel Corporation, Chandler, AZ, USAIEEE SCV Electron Devices Society, co-sponsored by IEEE SFBA Nanotechnology Council Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Abstract/bioPresentation Slides

November 2011 Half-Day Symposium

Nov. 4, 2011

Current Status and Future Directions of Non‐Volatile Memory Technology Invited Speakers:Dr. Gurtej Sandhu, MicronDr. Al Fazio, IntelDr. Chuck Dennison, OvonyxProfessor Michael Kozicki, Arizona State UniversityDr. Joshua Yang, HP Laboratories.IEEE Santa Clara Valley Electron Devices Society Location: Texas Instruments, Building E1, Conference Center,2900 Semiconductor Drive, Santa Clara, CA 95051. Announcement Speakers’ Biographies Talk abstract Agenda

October 2011

Oct. 13, 2011

The Variability Issues in Advanced CMOS: Random Dopant Fluctuation and Random Trap Fluctuation Speaker: Professor Steve S. Chung, Department of Electronics Engineering, National Chiao Tung University, Taiwan. IEEE Fellow, Distinguished LecturerIEEE SCV Electron Devices Society Distinguished Lecture Program Location: Kenna 214, Santa Clara University (direction linked below).Abstract/bioPresentation Slides

October 2011

Oct. 11, 2011

Carbon Electronics – From Material Synthesis to Circuit Demonstration Speaker: Professor H.-S. Philip Wong, Center for Integrated Systems and Department of Electrical Engineering, Stanford UniversityIEEE SCV Electron Devices Society and IEEE SFBA Nanotechnology Council Location: Texas Instruments Abstract/bioPresentation Slides

September 2011

Sept. 13, 2011

Metal interconnects for large-area power devices – physics, challenges, and solutions Speaker: Dr. Maxim Ershov, CTO, Silicon Frontline TechnologiesIEEE SCV Electron Devices Society Location: National SemiconductorAbstract/bio

August 2011

August 09, 2011

Graphene – Still Heading for Prime Time Speaker: Prof. Zhiping Yu, Institute of Microelectronics, Tsinghua University, Beijing, ChinaIEEE SCV Electron Devices Society Location: National Semiconductor.Abstract/bio Presentation Slides

June 2011

June 14, 2011

Simulation of Statistical Variability and Reliability: From TCAD to Statistical Circuit Simulation Speaker: Prof. Asen Asenov, FIEEE, FRSE; Leader of the Device Modeling Group, University of Glasgow; CEO of Gold Standard Simulations LtdIEEE SCV Electron Devices Society and IEEE SFBA Nanotechnology Council Location: National Semiconductor Abstract/bioPresentation Slides

May 2011

May 10, 2011

Characterization and Modeling of NBTI Stress, Recovery, Material Dependence and AC Degradation Using R-D Framework Speaker: Professor Souvik Mahapatra, Department of Electrical Engineering, IIT Bombay, IndiaIEEE SCV Electron Devices Society Location: National Semiconductor Abstract/bio Location map and directions

April 2011

April 14, 2011

Future ESD Challenges for IC Components and Systems Speaker: Dr. Charvaka Duvvury, Texas Instruments (Dallas, USA), EDS Distinguished Lecturer IEEE SCV Electron Devices Society Distinguished Lecture, cohosted by Stanford IEEE and TCAD group Location: Stanford University, Paul G. Allen Building Annex, Auditorium 101 Abstract/bio Presentation Slides

April 2011

April 5, 2011

The History of Flash Memory Technology and What Lies Ahead Speaker: Ishai Naveh, Adesto Technologies IEEE SCV Electron Devices Society Location: National SemiconductorAbstract/bio

March 2011

Mar. 1, 2011

Lithography Options for 22nm and Beyond Speaker: Dr. Geert Vandenberghe, imec IEEE SCV Electron Devices Society Location: National Semiconductor Abstract/bio

Feb 2011

Feb. 8, 2011

Photovoltaic Module Reliability and Failure Analysis: Enduring a storm Dr. Glenn Alers, University of California at Santa Cruz IEEE SCV Electron Devices Society, co-sponsored by IEEE SCV Reliability Society Location: National Semiconductor Abstract/bioSpeaker slides

Jan 2011

Jan. 11, 2011

Mechanical Computing Redux: Relays for Integrated Circuit Applications Prof. Tsu-Jae King Liu, Dept. of EECS, UC Berkeley IEEE SCV Electron Devices Society Location: National Semiconductor Abstract/bio

Dec 2010

Dec. 2, 2010

Millibits to Terrabits per second and Beyond – Over 60 Years of Innovation Dr. Renuka Jindal, Distinguished Lecture by IEEE Electron Devices Society President IEEE SCV Electron Devices Society Location: Santa Clara University Abstract/bio

Nov 2010

Nov 16, 2010

Resistive RAM: Technology and Market Opportunities Deepak Sekar, NuPGA Corporation IEEE SCV Electron Devices Society Location: National Semiconductor Abstract/bio Speaker slides

Nov 16, 2010

Nanoelectronics: Innovation and Implementation Half-day symposium by the Nanotechnology Council, co sponsored by EDS Location: National Semiconductor For available presentations

Oct 2010

Oct 12, 2010

Is it the End of the Road for Silicon in Power Management? Dr. Alex Lidow, CEO Efficient Power Conversion Corporation IEEE SCV EDS and PELS societies Location: National Semiconductor, Abstract/bio Speaker slides

Oct 18, 2010

Intellectual Property (IP) Primer for Entrepreneurs and Early-Stage Companies Jordan M. Becker, Partner, Perkins Coie IEEE SCV CAS and EDS societies Location:QualComm Santa Clara, Building B Abstract/bio Speaker slides

Oct 28, 2010

Second Annual IEEE-SCV Soft Error Rate (SER) Workshop  Chiate Lin, Intersil; Prof. Bharat Bhuva, Vanderbilt U.; Rick Wong, Cisco Systems;Dr Andy Mackie, Indium Corp.; Charles Slayman, Ops a la Carte; Dr. Brett Clark, Honeywell; Dr. Nelson Tam, Marvell  IEEE SCV CPMT/EDS/Rel societies Location: Cisco or webinar CPMT web page – slides etc.

Sept 2010

Sept 14, 2010

LDMOS – Technology and Applications Shekar Mallikarjunaswamy, Alpha Omega Semiconductor  IEEE SCV EDS seminar Location: National Semiconductor 2900 Semiconductor Drive , Santa Clara , CA 95052 Abstract/bio Speaker slides

Sept 28, 2010

The Makers of the Microchip: Creating the Planar Integrated Circuit, Establishing Silicon Valley David Brock, Research Fellow, Chemical Heritage Foundation Christophe Lecuyer, Principal Economic Analyst, UC Co-sponsored with IEEE SSC+CS Location: National Semiconductor Abstract/Bio/Registration

Aug 2010

Aug 10, 2010

3-D ICs: Motivation, Performance Analysis, Technology and Applications Dr. Krishna Saraswat, IEEE Fellow, Dept. of Electrical Engineering, Stanford University IEEE SCV EDS and CPMT societies Location: National Semiconductor, Building E-1, Conference Center Abstract/bio Speaker slides

July 2010

July 13, 2010

The Foundation of Today’s Digital World: The Triumph of the MOS Transistor Ross Bassett, Lewis M. Terman, Les Vadasz, David A. Hodges IEEE and CHM Location: Computer History Museum. Registration and further info

Jun 2010

Jun 7, 2010

New Driving Force for Electromigration in ULSI Interconnections and its implication to IC layout Dr. Cher Ming Tan – School of EEE, Nanyang Technological University, Singapore IEEE SCV EDS seminar Location: National Semiconductor Abstract/bio Speaker slides

Jun 18, 2010

Nanoscale Manipulation of Conductive Filaments in Solid-Electrolyte-Based-ReRAM Prof. Ming Liu, Institute of Microelectronics, Chinese Academy of Science (IMECAS), China. IEEE SCV EDS seminar Location: Santa Clara University 500 El Camino Real, Santa Clara, CA 95053 Abstract/bio Speaker slides

May 2010

May 20, 2010

Trends in Solar Cell Technology Dr. Betty Prince (New Energy Strategies International) IEEE SCV Solid-State Circuits (SSC) and Electron Devices Societies (EDS) Location: National Semiconductor IEEE SSC event page

May 11, 2010

Thoughts on Directions for Silicon Technology Development as We Approach the End of CMOS Scaling Tak H. Ning, IBM and IEEE Fellow, and co-author of the Taur & Ning textbook IEEE SCV EDS seminar Location: National Semiconductor 2900 Semiconductor Drive , Santa Clara , CA 95052 Abstract/bio Speaker Slides

Apr 2010

Apr 13, 2010

The Semiconductor Industry’s Nanoelectronics Research Initiative (NRI): Motivation and Overview Jeff Welser, IBM/Executive Director of NRI IEEE SCV EDS seminar Location: National Semiconductor, Building E-1, Conference Center Abstract/bio Speaker Slides

Mar 2010

Mar 16, 2010

2009 International Technology Roadmap for Semiconductors (ITRS) Update – Overview and Highlights Alan K. Allan – SEMATECH  IEEE SCV EDS seminar Location: National Semiconductor, Building E-1, Conference Center Abstract/bio Speaker slidesPhoto below with one of the first fifty 450 mm wafers ever (wafer made by Nippon Mining & Metals).

Feb 2010

Feb 16, 2010

High Frequency Characterization of Transistors J. Prasad, SuVolta Inc, Los Gatos, CA IEEE SCV EDS seminar Location: National Semiconductor, Building E-1, Conference Center Abstract/bio Click here for slides

Jan 2010

Jan 29, 2010

3D Interconnect – Shaping Future Technology Full-day symposium with many exciting talks Location: Hyatt Regency, 5101 Great America Pkwy, Santa Clara , CA 95054 Symposium: 9 AM – 5 PM Reception/Poster session: 5 – 6:30 PM Cost: Free. Refreshments and Lunch provided Click here for flyer  Click here for Agenda  Click here for Abstracts/bio.List of speakers: (slides available as posted) Matt Nowak, Qualcomm. Taming Cost and Design Challenges for High DensityThrough Silicon Stacking (TSS).  Click here for slides Xiaopeng Xu, Synopsys. Modeling Thermo-Mechanical Stress Impact on Performance and Reliability of 3D Integration Structures. Sesh_Ramaswami, Applied Materials. Journey Toward Process Convergence in TSV Technology Zvi Or-Bach, NuPGA. 3D FPGA – The Path to ASIC Density, Power, and Performance. Deepak C. Sekar, SanDisk. A 3D-IC Technology with Integrated Microfluidic Cooling. Arif Rahman, Xilinx, Inc. Technology Requirements and Standardization for 3-DSiP. Tom Ritzdorf, Semitool. Advances in Copper Fill for 3D Interconnect Applications. William Chen, ASE Group. 3D and More: A Renaissance in the Making. Raj Pendse, STATS ChipPAC 3D Integration: The Evolution of Device Architecture, Packaging, and Manufacturing Infrastructure C. Raman Kothandaraman, IBM Through Silicon Via (TSV) for 3D integration

For talks before Jan. 2010, please click here