Santa Clara Valley-San Francisco Chapter of Electron Devices Society

IEEE
Past Events

Aug 9th, 2016 Circuit Device Interactions and co-optimizations, from system and chip design to process integration – The secret sauce for complex SOC chips and SIPs in advanced technology nodes

IEEE SCV/SF Electron Devices Society August 9th, 2016 Seminar by Dr. John Hu, Director of Advanced Technology, Nvidia Corp., Santa Clara, CA

Circuit Device Interactions and co-optimizations, from system and chip design to process integration – The secret sauce for complex SOC chips and SIPs in advanced technology nodes 

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IEEE SCV/SF Electron Devices Society Seminar

Circuit Device Interactions and co-optimizations, from system and chip design to process integration – The secret sauce for complex SOC chips and SIPs in advanced technology nodes

Speaker: Dr. John Hu, Director of Advanced Technology, Nvidia Corp., Santa Clara, CA

Tuesday, August 9th, 2016

Time: 6:00 PM – 6:15 PM: Networking with food and refreshments
6:15 – 7:00 PM: Seminar 

Cost: Free

Location: Texas Instruments Building E Conference Center
2900 Semiconductor Dr., Santa Clara, CA 95052.
See the TI Building
location map and directions

Contact: Victor Cao

Web link: http://sites.ieee.org/scv-eds/

Abstract:

Technology scaling requires new disruptive processes, albeit with shrinking margins. New challenges are introduced in two area:  from the shrinking process margins and increased variations due to limitations in process,  or from the new device and new performance enhancements which introduced additional layout dependent effects as well as stronger design and process interactions.

On the other hand, more complex SOC designs that push the performance/power limits are also required to handle the increasing demand on computing power and functionality, with more stringent reliability requirements for the leading edge technologies due to advanced applications such as autonomous driving, cloud computing etc.

Design process interactions need to well characterized, and proper margins need to be designed in, to ensure down to dppb level failure rate. Product layout styles and selective usage by co-optimizations from system and chip level is necessary to achieve the best performance/power while mitigating parametric and systematic defect induced yield and reliability issues. Design for manufacturing/reliability and design process co-optimizations are also the necessary secret sauce for the advanced SOC chips and system in package,  to optimize for performance, power, area, cost and time to market in advanced process nodes.

Biography:

Dr. John Hu is currently director of advanced technology in Nvidia Corporation. Throughout his more than 20 years career, he has worked on technical and management roles across various area of the IC industry, including semiconductor materials, device fabrications and device physics, IC process technology development, interconnect technology and 3D chip integration, design methodology and design for manufacturing/reliability, test chips and technology driver products, and GPU/ CPU and mobile SOC technologies. John has served as the liaison for technology partnerships with various IC industry groups, companies and academics. John has also been board member of various organizations, as well as committee member and paper reviewer of technical meetings/journals.  Prior to Nvidia, John has worked in LSI Logic, Sun Microsystems and other companies. He has published more than 20 papers and has more than 10 patents granted or pending. John holds a BS degree from University of Science and Technology of China, and a PhD from Auburn University, in the field of solid state physics and microelectronics.


More information at the IEEE EDS Santa Clara Valley/San Francisco Joint Chapter Home Page
 http://sites.ieee.org/scv-eds/

Link to previous web page: http://www.ewh.ieee.org/r6/scv/eds/

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