Santa Clara Valley-San Francisco Chapter of Electron Devices Society

IEEE
Past Events

August 8th 2017 Recent Progress in Memory Technology Reliability

IEEE SCV-SF Electron Devices Society August 8th, 2017 Seminar by Dr. Bob Gleixner, Micron Technology Inc.

“Recent Progress in Memory Technology Reliability


IEEE SCV-SF Electron Devices Society Seminar “Recent Progress in Memory Technology Reliability”

 

Speaker: Dr. Bob Gleixner, Micron Technology Inc.

 

Date: Tuesday, August 8th, 2017

Time: 6:00 PM – 6:15 PM: Networking with food and refreshments

6:15 – 7:00 PM: Seminar 

Cost: Free

Location: Texas Instruments Building E Conference Center
2900 Semiconductor Dr., Santa Clara, CA 95052.
See the TI Building
location map and directions

Contact: Victor Cao

Web link: http://sites.ieee.org/scv-eds/

Abstract:

As they continue to pursue higher performance and densities at lower cost, semiconductor memory technologies have introduced novel materials and integration schemes from the cell to the packaging level. Understanding the reliability failure modes associated with these materials and processes is critical to providing a robust memory component. This presentation will review the major technology directions taking place in the areas of DRAM, NAND, and emerging memories. It will then review recent publications that identify the reliability concerns posed by these directions, with an emphasis on those that attempt to discern the underlying physics.

Biography:

Bob Gleixner received his Ph.D. degree in materials science from Stanford University in 1998. He then joined Intel and for the next ten years worked on reliability characterization of microprocessor, microdisplay, and non-volatile memory technologies and products. Starting in 2004 Bob’s work focused on developing and productizing advanced Phase Change Memory technologies, first at Intel and later with Numonyx. He joined Micron in 2010 as part of the Numonyx acquisition, where he is now a Distinguished Member of the Technology Staff. While at Micron he’s managed teams of silicon technology and product development engineers, with his main focus on the reliability of novel non-volatile memory technologies. He has published 13 technical papers and received 5 US patents.


More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

Subscribe or Invite your friends to sign up for our mailing list and get to hear about exciting electron-device relevant talks. We promise no spam and try to minimize email. You can unsubscribe easily.
http://sites.ieee.org/scv-eds/subscribe/

Follow us on social media

fb_icon_325x325 twitter_logo1-copy-256x256 256px-linkedin-svg_2 google-plus-logo-red-265px meetup