Santa Clara Valley-San Francisco Chapter of Electron Devices Society

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December 1st, 2016 On-Chip ESD Protection Design: Yesterday, Today, Tomorrow and Future

IEEE SCV-SF Electron Devices Society December 1st, 2016 Seminar by Prof. Albert Wang, University of California, Riverside

“On-Chip ESD Protection Design: Yesterday, Today, Tomorrow and Future” 


IEEE SCV-SF Electron Devices Society Seminar “On-Chip ESD Protection Design: Yesterday, Today, Tomorrow and Future”

Speaker: Prof. Albert Wang, Dept. of Electrical and Computer Engineering, University of California, Riverside

Thursday, Dec 1st, 2016

Time: 6:00 PM – 6:15 PM: Networking with food and refreshments

6:15 – 7:00 PM: Seminar 

Cost: Free

Location: Texas Instruments Building E Conference Center
2900 Semiconductor Dr., Santa Clara, CA 95052.
See the TI Building
location map and directions

Contact: Victor Cao

Web link: http://sites.ieee.org/scv-eds/

Abstract:

Electrostatic discharge (ESD) failure may be the most devastating reliability problem to ICs. On-chip ESD protection is therefore required for all ICs. As semiconductor technologies migrate to sub-28nm nodes and IC complexity continue to increase, ESD protection design emerges as a huge IC design challenge, particularly for multi-GHz RF and multi-Gbps high data rate ICs. Simply speaking, ESD protection design may be the biggest headache to IC designers and a killing factor to the time to market of new IC products. Vast efforts have been devoted to research and development in ESD protection designs. This talk will give a historical outline on ESD protection designs: yesterday, today, tomorrow and the future. The talk will start with discussing ESD protection basics and traditional ESD protection solutions, followed by a review on current ESD protection design status including mixed-mode ESD protection simulation-design techniques, low-parasitic ESD protection designs for RF and high-speed ICs, ESD-IC co-design techniques, field-programmable ESD protection and field-dispensable ESD protection solutions. The talk will continue to discuss the new CAD tool for full-chip ESD protection circuit design verification. Finally, exploratory future ESD protection concepts, including 3D above-IC ESD protection solutions, will be discussed.

Biography:

Albert Wang received the BSEE degree from Tsinghua University, China, and the PhD EE degree from The State University of New York at Buffalo in 1985 and 1996, respectively. He was with the National Semiconductor Corporation from 1995 to 1998. From 1998 to 2007, He was Professor of Electrical and Computer Engineering at the Illinois Institute of Technology. Since 2007, he has been a Professor of Electrical and Computer Engineering at University of California, Riverside. Wang is Director for the University of California system-wide Center for Ubiquitous Communications by Light (UC-Light) and co-Director for the SMIC-UCR-PKU Joint Center for ESD Protection Design. His research covers Mixed-Signal/RF ICs, Integrated Design-for-Reliability, 3D Heterogeneous Integration of Devices and ICs, IC CAD and Modelling, Biomedical Electronics, Emerging Devices and Circuits, and Visible Light Communications. Wang received the CAREER Award from the National Science Foundation in 2002. He is the author for the book “On-Chip ESD Protection for Integrated Circuits” (Kluwer, 2002). He published more than 240 peer-reviewed papers in the field and holds thirteen U.S. patents. Wang was Associated Editor for IEEE Transactions on Circuits and Systems I, Editor for IEEE Electron Device Letters, Associate Editor for IEEE Transactions on Circuits and Systems II, Guest Editor-in-Chief for the IEEE Transactions on Electron Devices and Guest Editor for IEEE Journal of Solid-State Circuits. He has been IEEE Distinguished Lecturer for the Electron Devices Society, the Circuits and Systems Society and the Solid-State Circuits Society. He is Jr. Past President (2016-2017) and was President (2014-2015) for the IEEE Electron Devices Society. He was Chair for the IEEE CAS Analog Signal Processing Technical Committee (ASPTC) and committee member for the SIA International Technology Roadmap for Semiconductor (ITRS). He was General Chair for IEEE RFIC Symposium (2016). He served as committee member for many IEEE conferences, e.g., IEDM, BCTM, ASICON, IEDST, ICSICT, CICC, RFIC, APC-CAS, ASP-DAC, ISCAS, IPFA, ICEMAC, NewCAS, ISTC, IRPS, AP-RASC, MAPE, EDSSC, MIEL, etc. He is an IEEE Fellow.


More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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