Nov 11th, 2016 Annual Symposium – Device Circuit Interaction in Advanced Technology Nodes
IEEE SCV-SF EDS Annual Symposium
Device Circuit Interaction in Advanced Technology Nodes
Friday Nov 11th 2016, 1PM-5:30PM
Texas Instruments, Building E Auditorium, 2900 Semiconductor Drive, Santa Clara, CA
Map and direction to venue
Organized by the IEEE Santa Clara Valley Chapter of Electron Device Society, http://site.ieee.org/scv-eds/
Co-sponsored by: IEEE Santa Clara Valley Reliability Chapter, IEEE CPMT Chapter of San Francisco Bay Area, SF Bay Area Nanotechnology Council, IEEE Santa Clara Valley Solid State Circuits Society Chapter
This seminar will cover device, circuit and system/architecture level interactions and co-optimizations in advanced technology nodes.
Agenda:
1:00PM Registration and Networking
1:30PM Hardware for Deep Learning, Dr. William J. Dally, Chief Scientist and Sr. VP of Research, NVIDIA, and Stanford Professor
2:15PM Design-Technology Co-Optimization for 5nm Node and Beyond, Dr. Victor Moroz, Scientist, Synopsys
3:00PM Chip Design and Process Co-optimizations, Design for Manufacturing/Reliability in Advanced Technology Nodes, Dr. John Hu, Director, Advanced Technology, Nvidia Corp
3:45PM Break and networking
4:00PM Process Requirements for Integrated Power Circuits, Dr. Kevin Scoones, Fellow, Texas Instruments
4:45PM 2.5D/3D Package Integration: Technology Trends, Challenges and Applications, Dr. Suresh Ramalingam, Fellow, Advanced Packaging, Xilinx
Interactive Q/A discussions will also be available after each talk.
Note: No refunds will be made in event of cancellation of the registration by an attendee.
More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page
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