Santa Clara Valley-San Francisco Chapter of Electron Devices Society

IEEE
Past Events

July 11th, 2017 System Level ESD: A New Focus

IEEE SCV-SF Electron Devices Society July 11th, 2017 Distinguished Lecturer (DL) Seminar by Dr. Charvaka Duvvury, ESD Consulting

 

​We would like to thank the IEEE-EDS Distinguished Lecturer (DL) Program, IEEE CPMT Chapter SF BA, IEEE Santa Clara Valley Reliability Chapter,
IEEE Circuits and Systems Society Santa Clara Valley Chapter, and IEEE Solid State Circuits Society Santa Clara Valley Chapter for cosponsoring ​this event.

“System Level ESD: A New Focus


IEEE SCV-SF Electron Devices Society Seminar “System Level ESD: A New Focus”

 

Speaker: Dr. Charvaka Duvvury, ESD Consulting

Date: Tuesday, July 11th, 2017

Time: 6:00 PM – 6:15 PM: Networking with food and refreshments

6:15 – 7:00 PM: Seminar 

Cost: Free

Location: Texas Instruments Building E Conference Center
2900 Semiconductor Dr., Santa Clara, CA 95052.
See the TI Building
location map and directions

Contact: Victor Cao

Web link: http://sites.ieee.org/scv-eds/

Abstract:

With the continued scaling of technologies the ESD qualification has become a major challenge. This is mainly due to the demand for higher speed circuits, mostly implemented in large high pin count packages, and increased SoC applications. It has already been established that these are having consequences for ESD qualification requiring a new thrust to change the component ESD target levels. At the same time system level ESD has become much more important and combining with the new lower ESD target levels system protection is demanding a more thorough understanding with a co-design approach. This is especially the case for USB and HDMI interfaces along with RF applications. This seminar will give a brief roadmap for component level ESD levels followed by an overview of the system level ESD protection challenges. The concept of “system-efficient-ESD-design” (SEED) will be presented to describe a more desirable approach to achieve robust systems while preserving signal integrity. Examples of designing with simulation approaches for both hard and soft ESD failures will be introduced.

Biography:

Charvaka Duvvury was a Texas Instruments fellow while he worked in the Silicon Technology Development group. Charvaka is also a life fellow of the IEEE. He is currently working as a technical consultant on ESD design methods and ESD qualification support. Charvaka received his PhD in engineering science from the University of Toledo. He has published over 150 papers in technical journals and conferences and holds more than 75 patents. He is a recipient of the IEEE EDS Education Award (2013), Outstanding Contributions Award from the EOS/ESD Symposium (1990), Outstanding Industry Liaison Award twice from the Semiconductor Research Council (1994 and 2012), and IRPS Outstanding Paper Award as well as several Best Paper Awards from the ESD Symposium. He has been a Board of Director of the ESD Association since 1997. Charvaka also served in the Technical Program Committees of both IEDM and IRPS. He was a contributing editor for the IEEE Transactions on Device and Materials Reliability (TDMR) from 2001-2011. He is a co-founder and has been co-chair of the Industry Council on ESD Target Levels since 2006.


More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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