Santa Clara Valley-San Francisco Chapter of Electron Devices Society

IEEE
Past Events

June 14th, 2016 High Frequency Characterization of Transistors

IEEE SCV Electron Devices Society June 14th, 2016 Seminar by Dr. Jayasimha Prasad, Device/Process Integration Engineer, Foveon Inc, San Jose CA

“High Frequency Characterization of Transistors”

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IEEE SCV Electron Devices Society Seminar
“High Frequency Characterization of Transistors”

Speaker: Dr. Jayasimha Prasad, Device/Process Integration Engineer, Foveon Inc, San Jose CA

Tuesday, June 14th, 2016

Time: 6:00 PM – 6:15 PM: Networking with food and refreshments
6:15 – 7:00 PM: Seminar 

Cost: Free
Location: Texas Instruments Building E Conference Center

2900 Semiconductor Dr., Santa Clara, CA 95052.
See the TI Building
location map and directions
Contact: Victor Cao

Web link: http://sites.ieee.org/scv-eds/

Abstract:

As CMOS devices continue to scale, the high-frequency figures of merit for CMOS devices have reached several hundred GHz. People are now using CMOS for microwave applications. The high frequency performance of SiGe HBTs has reached a high of 1THz. The figures of merit such as Ft, Fmax and Noise Figure are becoming very important. Device Engineers generally look at D.C parametric test data and if they look good, they simply assume that the device will meet high frequency specs. On the other hand, Microwave Engineers pay attention to Ft, Fmax, Maximum Available Gain (MAG) etc., and don’t care too much about the D.C parametric data. The reason for this dichotomy is that the Device Engineer is not exposed to microwave characterization and the microwave engineer is not completely familiar with various methods used in D.C characterization of the devices.
This talk will begin with a brief introduction to S-parameters and the Smith Chart so that everyone can follow the talk. We will show how to extract Ft and Fmax from the measured S-parameters. Stability becomes an important issue when we are maximizing the gain of a device. The various gains, namely, Maximum Available Gain (MAG), Maximum Stable Gain (MSG) and Mason’s Unilateral Gain (U) will be covered. Next, we will describe the Vector Network Analyzer, Calibration methods, measurements and de-embedding the on-wafer S-parameters from the layout parasitics. We will also show how to extract series resistances and capacitances from the measured S-parameters.

Biography:

Prasad has worked on various device technologies starting from Germanium Transistors, VMOS, EEPROM, GaAs and SiGe based Heterojunction Bipolar Technologies, SiGe BiCMOS, LDMOS, VDMOS, and Complementary JFET technology. He has held various engineering/management positions at American Microsystems, National Semiconductor, Tektronix, Maxim, SuVolta,Volterra,and Micrel Semiconductor. He was the first in the world to demonstrate a 60GHz InGaP HBT technology with 28ps gate delay. He was instrumental in developing very high speed device technologies at Tektronix and was promoted to the position of Tektronix Fellow. He is an IEEE Life Fellow and an EDS Distinguished Lecturer. He has served in the technical committees of IEDM and BCTM. He has published several papers and holds many patents. He obtained his Ph.D in Electrical Engineering from Oregon State University, Corvallis. He is currently working on CMOS image sensor technology at Foveon Inc, San Jose.