Santa Clara Valley-San Francisco Chapter of Electron Devices Society

IEEE
Past Events

June 24th, 2015 “A Unified Compact Model for Generic HEMTs”

June 24th, 2015

A Unified Compact Model for Generic HEMTs

Speaker: Prof. X. Zhou, DL, Nanyang Technological University, Singapore

Abstract:

III-V channel field-effect transistors (FETs), such as GaN-based high electron-mobility transistors (HEMTs), have emerged as promising candidates for future generation high-frequency, high-voltage, and high-power ULSI applications.  Development of a compact model for HEMTs in III-V/Si co-integrated hybrid circuit design is becoming an urgent need for semiconductor industry.  This talk presents a unified compact model for generic GaN-based HEMTs, which has been validated with the exact numerical solutions for a wide range of device parameters and verified with experimental data of sub-100-nm gate lengths.  The model is based on unified regional modeling (URM) of the 2-dimensional electron gas (2DEG) charge density, including the two lowest subbands of the quantum well (QW) in the active region, and extending to the moderate-inversion and subthreshold regions of operation in a single-piece formulation.  The 2DEG charge density model is adopted in the surface-potential (SP)-based model for conventional bulk/SOI/multigate MOSFETs, which makes it compatible and scalable for future III-V/Si co-integrated generations.  In this talk, fundamentals in compact modeling of generic FETs are reviewed in the context of the URM approach, and its extension to modeling the 2DEG in generic HEMT devices, including triangular-QW GaN-based and rectangular-QW InGaAs-based HEMTs.  SOI-based formulations for thick-body effects are extended to subthreshold modeling, and quasi-2D field solutions are adopted in the drift-diffusion transport with new interpretation of velocity saturation for geometry/bias-dependent “QB-mobility”.  HEMT-specific features will also be discussed, such as source/drain access resistances and trap modeling for gate/drain-lag effects (“current collapse”).

Biography:

Dr. Xing Zhou obtained his B.E. degree in electrical engineering from Tsinghua University in 1983, M.S. and Ph.D. degrees in electrical engineering from the University of Rochester in 1987 and 1990, respectively.  He has been with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore since 1992.  His past research interests include Monte Carlo simulation of photocarrier transport and ultrafast phenomena as well as mixed-mode circuit simulation and CAD tool development.  His recent research mainly focuses on nanoscale CMOS compact model development.  His research group has been developing a unified core model for nanoscale bulk, SOI, double-gate, nanowire CMOS, as well as III-V HEMTs.  He has given more than 140 IEEE EDS distinguished lectures and invited talks at various universities as well as industry and research institutions.  He was visiting professor to Stanford University (1997/2001), Hiroshima University (2003), Universiti Teknologi Malaysia (2007), Fudan University (2011/2012/2014), and Tokyo Institute of Technology (2011/2012).  He is the founding chair for the Workshop on Compact Modeling (WCM) in association with the NSTI Nanotechnology Conference since 2002.  Dr. Zhou is an elected member-at-large of the IEEE EDS AdCom/BoG in 2004–2009 and 2011–2016, vice-president for Regions/Chapters in 2013–2015.  He was a guest Editor-in-Chief for the special issue of the IEEE Transactions on Electron Devices (Feb. 2014) on compact modeling of emerging devices.  He has been a senior member of IEEE since 1999, an EDS distinguished lecturer since 2000, and an editor for the IEEE Electron Device Letters since 2007.

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