Santa Clara Valley-San Francisco Chapter of Electron Devices Society

IEEE
Past Events

October 11th, 2016 Time-Zero and Time-Dependent Variability in Advanced CMOS

IEEE SCV-SF Electron Devices Society October 11th, 2016 Seminar by Dr. Jeffrey T. Watt, Intel Fellow, Intel Corp., Santa Clara, CA

Time-Zero and Time-Dependent Variability in Advanced CMOS


Speaker: Dr. Jeffrey T. Watt, Intel Fellow, Intel Corp., Santa Clara, CA

Tuesday, October 11th, 2016

Time: 6:00 PM – 6:15 PM: Networking with food and refreshments
6:15 – 7:00 PM: Seminar 

Cost: Free

Location: Texas Instruments Building E Conference Center
2900 Semiconductor Dr., Santa Clara, CA 95052.
See the TI
Buildinglocation map and directions

Contact: Victor Cao

Web link: http://sites.ieee.org/scv-eds/

Abstract:

Aggressive CMOS device scaling has enabled dramatic growth in the performance, capacity and capability of VLSI products. It has also led to increases in transistor and circuit variability as a result of dimensional scaling, voltage scaling and the introduction of new materials and structures. Both variability at the beginning of product life (time-zero variability) and increased variability caused by device aging (time-dependent variability) must be understood and accounted for in product design to ensure acceptable yield and lifetime. In this talk, an array-based approach which has been developed to characterize transistor variability will be presented. Time-zero and time-dependent variability results will be shown for an advanced high-K/metal-gate technology. Modeling and simulation methodologies which have been used to accurately account for variability effects will be reviewed.

Biography:

Jeffrey (Jeff) T. Watt is an Intel Fellow and the architect for field-programmable gate array (FPGA) process technology in the Programmable Solutions Group at Intel Corporation. He is responsible for device, interconnect and radio frequency (RF) modeling; technology test chip development and wafer-level characterization; and on-chip electrostatic discharge (ESD) protection. Watt also contributes to the office of the group’s chief technology officer, with responsibility for initiatives in the area of novel process technology development for FPGA applications.

Watt joined Intel in 2015 with the acquisition of Altera Corporation, where he had a similar role as an Altera Fellow responsible for technology development. During his 13-year tenure at Altera, Watt led the delivery of models and ESD solutions for six generations of process technology, from 90-nanometer (90nm) to 14nm. He also led the development of multiple new capabilities in the areas of statistical simulation, aging simulation, RF models and test structures for model validation.

Before joining Altera in 2002, Watt spent 13 years at Cypress Semiconductor. As device engineering manager at Cypress, he led the development of transistor processes from 0.65-micron to 90nm technology.

Watt has been granted more than 70 U.S. patents in the areas of CMOS processing, device structures, circuits and ESD protection. He has also authored or co-authored more than 25 technical papers on related topics.

Watt holds a bachelor’s degree in electrical engineering from Queen’s University at Kingston in Ontario, Canada; and a master’s degree and Ph.D. in electrical engineering from Stanford University. He has served on the technical program committees of the Symposium on VLSI Technology and the International Conference on Simulation of Semiconductor Processes and Devices. He is a senior member of the Institute of Electrical and Electronics Engineers and a past chairman of the Santa Clara Valley Chapter of the Electron Devices Society. Watt was named an Altera Fellow in 2012 and an Intel Fellow in 2016.


More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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