IEEE

Tutorial on LDPC Decoding

IEEE Tutorial on LDPC Decoding, VLSI Architectures and Implementations

Speakers: Dr. Ned Varnica, Marvell Semiconductor and Dr. Kiran Gunnam, HGST

Date: Wednesday, August 6, 2014

Time: 7:00 pm – 9:30 pm

Location: Flash Memory Summit Conference, Santa Clara Convention Center, Santa Clara

 

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Ned and Kiran’s Slide Decks:

  1. Module 1: LDPC Decoding (Ned Varnica)
  2. Module 2: VLSI Architectures and Implementation (Kiran Gunnam)

 

Abstract:

LDPC codes are now being used in Hard disk drive read channels, Wireless (IEEE 802.11n/ IEEE 802.11ac, IEEE 802.16e WiMax), 10-GB, DVB-S2, and more recently in Flash SSD. Tutorial’s target audience is system engineers and design engineers. Tutorial has two parts, first module is focused on LDPC Decoding and second module is focused on VLSI Architectures and Implementations.

 

Tutorial overview

Module 1 LDPC Decoding

1.1) LDPC codes

1.2) Hard decision decoding

1.3) LLR basics and LLR generation for soft decoding for Flash memory channel

1.4) Soft decoding and Min-Sum Algorithm

1.5) LDPC decoder performance characteristics, trapping sets and error floor

1.6) Basics of Code Structures for Efficient hardware.

 

Module 2 VLSI Architectures and Implementations

2.1) Check Node Unit Design and Value-reuse property

2.2) Non-layered decoder architecture

a. Block serial processing
b. Translating throughput requirement to H matrix parameters and edge parallelization

2.3) Layered decoder architecture

a. Block serial processing
b. Block serial processing for irregular H matrices, scheduling of decoder processing
c. Block parallel processing
d. Translating throughput requirement to H matrix parameters and edge parallelization
e. Case study of decoders for 802.11n and Flash channel

2.4) Error floor mitigation schemes

 

Speakers

  • Ned VarnicaMarvell Semiconductor

Ned Varnica received the B.S. degree in Electrical Engineering in 2000 from School of Electrical Engineering, University of Belgrade, Serbia, the M.S. degree in 2001 and Ph.D. in 2005 both from Harvard  University, Cambridge, Massachusetts.

Since 2005 he has been with Marvell Semiconductor Inc, Santa Clara, California. He held short-term research positions at Maxtor Corporation, Shrewsbury, Massachusetts in 2002 and Lucent Bell Labs, Murray Hill, New Jersey in 2004. He spent the summer of 2003 as a visiting researcher at University of Hawaii at Manoa, Honolulu. His research interests are in the areas of communication theory, information theory, channel and source coding and their applications to digital data storage and wireless communications.

Dr. Varnica received the Best Student of the Class Award from the Department of Communications at the School of Electrical Engineering, University of Belgrade in 2000.  He is a co-recipient, with A. Kavcic and X. Ma, of the 2005 IEEE Best Paper Award in Signal Processing and Coding for Data Storage.

  • Kiran Gunnam, HGST

Kiran Gunnam is currently a Technologist at HGST Research, where he works on storage architectures. He was previously Director of Engineering at Violin Memory and also held research and development positions at NVIDIA, LSI, Marvell Semiconductor, and Intel. He received his MSEE and PhD in Computer Engineering from Texas A&M University. His PhD research contributed several key innovations in advanced error correction systems based on low-density parity-check codes (LDPC) and led to several industry designs. He has 51 issued US patents and several pending applications and invention disclosures. He is also an IEEE Distinguished Speaker and Plenary Speaker for more than 14 events and international conferences.

 

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