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Moore’s Law scaling impact on Silicon Reliability – A system based holistic approach

Abstract
While Moore’s Law continues to provide scaling benefits to enable SoCs, it poses major Reliability and Manufacturing challenges. Supply voltages and current densities are scaling at a slower pace than device dimensions. As a result, TDDB and Electromigration lifetimes are degrading, posing major reliability hurdles at advanced nodes (14nm and beyond). The talk will elaborate on technology scaling and highlight the major Silicon reliability degradation mechanisms.
Accurate estimation of system level reliability requires a thorough understanding of the failure modes of the various components and modules that make up the system and their interactions with each other. A clear definition of Mission profile is necessary to project the test data to use conditions. With the increasing use of smart devices, mobile technologies and ubiquitous computing, the usage scenarios are getting increasingly complex. As a result, JEDEC based standard Qualification methodologies for components cannot be relied upon to ensure reliability at system level during field usage.
A comprehensive Silicon Reliability framework using a system based holistic approach will be discussed. This framework comprehends user environment and usage scenarios at system level to make reliability projections more meaningful. “Design for Reliability” (DfR) approaches will be presented to enable performance without compromising reliability.
This talk will also introduce the methodology of “Reliability Budgeting” and show how this can be applied at chip level and then at the system level using a tops-down and bottoms-up approach to realize an optimum trade-off between performance and reliability.

 

Bio- Amit Marathe
Amit Marathe earned his M.S. and Ph.D. in Materials Science and Engineering from the University of California, Berkeley in May 1991 and August 1996 respectively.
Amit joined AMD in Sunnyvale CA after graduation and then GlobalFoundries in 2009. At AMD and GF, he was leading and managing the Technology & Reliability Development Organization. In 2011, Amit joined Microsoft and was managing the Silicon/Packaging Operations & Reliability Org for all of Microsoft Hardware. Amit joined Google in 2016 where he is heading the SOC/Module Technology and Reliability Engineering group within Consumer Hardware Org at
Google.
Amit has co-authored over 40 technical research publications as well as a chapter in a book on Moore’s Law Scaling Reliability Challenges. He has chaired sessions at IRPS Conf. and presented “Year in Review” on System Reliability. He also gave a tutorial on the same topic in 2018 IRPS. He has given keynotes at other International Conferences. He is a co-inventor of over 15 patents granted and over 50 pending US patents in the area of technology & reliability
development.
 
Food sponsored by I.C.E. Labs, ISO 9001 & 17025 Reliability Test Lab, www.icenginc.com
Attendance to this seminar will count towards professional development hours for IEEE, ASQ. Please feel free to forward this message to your friends and colleagues.
Agenda
Check-in and pizza at 6:15 – 6:45 PM.
Presentation at 6:45 – 7:45 PM.
Q&A at 7:45PM

Thursday, June 14, 2018

Moore’s Law scaling impact on Silicon Reliability – A system based holistic approach

Sponsored by IEEE SCV Reliability Chapter
Time: 6:15 pm – 8:00 pm
Qualcomm, Inc. Building-B Cafeteria, 

 
 
 

Thursday, Sept 13, 2018
Fractional Failure and Its Application in Reliability Engineering

Sponsored by IEEE SCV Reliability Chapter
Time: 6:15 pm – 8:00 pm
Qualcomm, Inc. Building-B Cafeteria,