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Reliability characterization of discrete devices and modeling circuit level aging in advanced CMOS technologies

Thursday, January 10, 2019

Abstract

Scaled transistor technologies encounter additional reliability challenges besides bias temperature instability, time dependent dielectric breakdown and hot carrier degradation. Time-zero variability and variability induced by device aging is a growing concern which needs to be modeled using stochastic processes. The physical nature of the stochastic process remains under debate and to support model development efforts large statistical data sets are essential. In addition, self-heating during reliability testing can be observed in novel device structures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices and needs proper attention. Apart from model development for the individual reliability mechanisms, variability and self-heating, it is critical to provide a platform integrating their impact for a circuit level assessment. In this presentation we discuss how to obtain stochastic BTI data for discrete SRAM and logic device beyond 3s, address silicon validated modeling of degradation in RO/SRAM plus explore self-heating effects in FinFET and SOI devices.

Speaker’s Bio:

Tanya Nigam is a Fellow at GLOBALFOUNDRIES. She obtained her PHD from KU LEUVEN in 1999 in the area of gate oxide breakdown. Since then she has worked on various challenges in the area of FEOL Reliability which include TDDB, BTI, HCI, LDMOS devices and correlation of device level reliability to product reliability. She continues to focus on device to product correlation for different failure modes in scaled technologies. She has co-authored 65+ papers in Journals and Conferences.

 

Thursday, January 10, 2019

Reliability characterization of discrete devices and modeling circuit level aging in advanced CMOS technologies

Sponsored by IEEE SCV Reliability Chapter

Time: 6:15 pm – 8:00 pm

Qualcomm Inc. Building-B Cafeteria
3165 Kifer Road
Santa Clara, CA 95051 United States