July 19,2012

A Wide Common-Mode Fully-Adaptive Multi-Standard 12.5Gb/s Backplane Transceiver in 28nm CMOS

Speaker: Jafar Savoj ,Xilinx, Inc., San Jose, CA

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This talk describes the design of a fully-adaptive backplane transceiver embedded in a state-of-the-art, low-leakage, 28nm CMOS FPGA. The wide common mode receive AFE utilizes a three-stage CTLE to provide selective frequency boost for long-tail ISI cancellation. A 5-tap speculative DFE removes the immediate post-cursor ISI. Both CTLE and DFE are fully adaptive using sign-sign LMS algorithm. A novel clocking technique uses wideband LC and ring oscillators for reliable clocking from 0.6-12.5Gb/s operation. The transmitter utilizes a 3-tap FIR and provides flexibility for supply and ground referenced operation. The transceiver achieves BER < 10^-15 over a 33dB-loss backplane at 12.5Gb/s and over multiple channels with 10G-KR characteristics at 10.3125Gb/s.


Jafar Savoj received the B.Sc. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1996, and the M.Sc. and Ph.D. degrees in electrical engineering from the University of California, Los Angeles, in 1998 and 2001, respectively. His Ph.D. research yielded the first 10-Gb/s clock and data recovery circuit in CMOS technology.

Dr. Savoj’s areas of expertise include technology and product development for wireless, wireline, and analog systems. He is currently an Engineering Director with the Serdes Technology Group at Xilinx, San Jose, CA, and leads high-speed, low-power wireline transceiver development for FPGA applications. From 2008 to 2010, he was with Qualcomm, Santa Clara, CA, and led the advanced technology development group for wireless connectivity. He was responsible for development of WLAN and Near Field Communication (NFC) transceivers, and low power chip-to-chip interfaces for mobile platforms. From 2005 to 2008, he was a principal engineer at Rambus, where he developed ultra-high-speed data converters for software programmable wireline transceivers. Prior to that, he held design engineering positions at Marvell Semiconductor, Santa Clara, CA, focusing on fiber channel and Gigabit Ethernet transceivers; and at Transpectrum, Los Angeles, CA, architecting 10-Gb/s and 40-Gb/s optical transceivers in CMOS technology. He held a lecturing position at Stanford University in 2004. He is the author of High-Speed CMOS Circuits for Optical Receivers (Kluwer, 2001).

Dr. Savoj was a recipient of the IEEE Solid-State Circuits Society Predoctoral Fellowship for 2000–2001, and the Beatrice Winner Award for Editorial Excellence at the 2001 ISSCC, and the Design Contest Award of the 2001 Design Automation Conference. He serves as a technical program committee member of ISSCC (Analog Subcommittee). He served as a technical program committee member of the IEEE Custom Integrated Circuits Conference (CICC) from 2001 to 2007 and the IEEE Symposium on VLSI Circuits from 2007 to 2011. He was an Associate Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS from 2008 to 2011 and a Guest Editor for the Journal in 2005, 2006 and 2011.



SCV SSCS Technical meetings are typically held on The THIRD Thursday of each month at:
Texas Instruments Building E Auditorium
2900 Semiconductor Dr., Santa Clara, CA 95051 Directions and Map.  Refreshments are provided at 6:00 PM and the talk typically begins at 6:30 PM.Donations requested to partially cover food cost.The talks are open to everyone, feel free to join us even if you are not an IEEE member yet.


to the Santa Clara Valley chapter of the Solid State Circuits Society


November 2017

Next Meeting

Dec. 1, 2017

Distinguished Lecturer Seminar

“Recent Developments in Transceiver SoC Design for Next Generation Optical Networks” by Prof. Patrick Yue, HKUST

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