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Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond


ABSTRACT

The economics of CMOS scaling remain lucrative with 7-nm mobile SoCs expected to be commercialized in 2018. Driven by careful design/technology co-optimization, modest reduction in fin, gate, and interconnect pitch as well as process innovations continue to offer compelling node-to-node power, performance, area, and cost benefits to advance logic and SRAM to the next foundry node. However, analog/mixed-signal circuits do not fully realize these improvements. They become more cumbersome to design, having worse parasitic resistance and capacitance, stronger layout-dependent effects, and layout growth in some situations. Furthermore, early adopters of these cutting-edge finFET nodes must cope with the complications of design concurrent with technology development for shorter product time-to-market. We provide an overview of the key process technology elements enabling 7 nm and beyond to address analog/mixed-signal design challenges. From this insight, we offer layout guidelines aimed to reduce design vulnerability to technology and model immaturity.

Date and Time

Location

  • 14820 Northeast 36th Street
  • Redmond, Washington
  • United States 98052
  • Building: 99
  • Room Number: 1919

Staticmap?size=250x200&sensor=false&zoom=14&markers=47.641402917122%2c 122

Contact

Registration

  • No Admission Charge
  • Starts 20 November 2018 06:14 PM
  • Ends 11 December 2018 05:00 PM
  • All times are America/Los_Angeles

 

Speakers

Dr. Alvin Loke

Dr. Alvin Loke of Qualcomm

 

Topic:

Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond

 

Agenda

ABSTRACT

 

The economics of CMOS scaling remain lucrative with 7-nm mobile SoCs expected to be commercialized in 2018. Driven by careful design/technology co-optimization, modest reduction in fin, gate, and interconnect pitch as well as process innovations continue to offer compelling node-to-node power, performance, area, and cost benefits to advance logic and SRAM to the next foundry node. However, analog/mixed-signal circuits do not fully realize these improvements. They become more cumbersome to design, having worse parasitic resistance and capacitance, stronger layout-dependent effects, and layout growth in some situations. Furthermore, early adopters of these cutting-edge finFET nodes must cope with the complications of design concurrent with technology development for shorter product time-to-market. We provide an overview of the key process technology elements enabling 7 nm and beyond to address analog/mixed-signal design challenges. From this insight, we offer layout guidelines aimed to reduce design vulnerability to technology and model immaturity.

 

 

 


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Upcoming Events

  1. Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond

    December 11 @ 6:00 pm - 7:00 pm
  2. IEEE Seattle Excom Dece 2018

    December 11 @ 7:00 pm - 9:00 pm
  3. IEEE Seattle Section Excom

    December 11 @ 7:00 pm - 9:00 pm