SF Bay Area Nanotechnology Council

IEEE

IEEE SFBA Nanotechnology Council Chapter 13th Annual Full Day Symposium

“Nanotechnology in : The Environment, Advanced Batteries, Clean Energy”

May 16, 2017 8:30AM – 4:30 PM

SEMI Global Headquarters, 673 South Milpitas Boulevard, Milpitas, CA 95035

Register here

This symposium brings together leading academic, government and industry experts to discuss the innovation opportunities and technical challenges associated with the deployment of nanotechnology in the  above areas. Presentation Topics and Speakers include:

Nano Material Toxicity

Marie-Noele Croteau, USGS

Regulating Nano Toxicity

Jeffrey Wong, California Environmental Protection Agency

Hydrogen Storage

Jen Dionne, Stanford University

Carbon Dioxide Capture

Robert Aines, Livermore

Nanostructured, Bio-Derived Materials for Next-Generation Li-ion Batteries

Brennan Campbell, NexTech Batteries && Robert Ionescu, HP Labs

Carbon Nanotube Batteries for Solar Grid Storage & Electric Vehicles

John Wong, CTO, Magi Scitech

Job Seeker assistance will be available at this event, including a table with CVs and resumes available for people to pick up and an “Announcement Slide” which will be projected during the initial networking portion of the day. Job seekers, please bring your resumes to display on said table, send a one line description to be displayed on the “Announcement Slide” to SFBA.Nano.Jobs@gmail.com by May 14.

Register here

 Sponsors Include:


TITLE: Fully Inkjet-Printed RRAM Memory Circuits for Solution-Processed Electronics

SPEAKER: Jeremy Smith, PhD., U.C. Berkeley

Tuesday, April 18, 2017  11:30 AM – 1:00  pm

Texas Instruments (TI) Auditorium E-1
2900 Semiconductor Drive
Santa Clara, CA map

Cost $6, discount for IEEE Members, Students & Unemployed. Please register here.

ABSTRACT:

Inkjet printing provides a convenient, digital, additive manufacturing process to demonstrate the compatibility of solution-processed electronic materials suitable for flexible electronics, roll-to-roll processing, and large-area electronics.

This study also highlights some of the challenges of controlling film formation, nanoparticle ink development, and materials interactions in a realistic situation. I will discuss the use of sol-gel oxides and metal nanoparticle inks in a 3D printer for fabricating novel transistors and RRAM memory devices. In particular, using fully printed thin-film transistors (TFT),

I have studied several interface effects that are critical for device operation both in terms of the print morphology and also electrical injection and back surface effects. The dielectric, in this case ZrO2, was found to be very sensitive to the sol-gel drying conditions, which are not always well controlled during printing.

In the case of memory devices, resistive switching was employed in the Ag/ZrO2/Au system to fabricate printable RRAM memory arrays. These arrays can be operated as content addressable memory, which has many applications in pattern matching, image recognition, and synaptic-like memory behavior. However, controlling the uniformity of switching, especially in printed devices, is an important challenge. In conclusion, we show that knowledge of component materials, processing effects, and interactions of materials within a device are all critical to advancing the field of printed electronics.

Image by A13ean Use licensed under the Creative Commons Attribution

SPEAKER BIOGRAPHY:

Jeremy Smith received his MSci degree in Materials Science from the University of Cambridge in 2007 and his PhD in the Physics Department at Imperial College London. His research, under the supervision of Prof. Thomas D. Anthopoulos, was focused on the development of high mobility organic field-effect transistors with a particular interest in the links between thin-film morphology and charge transport.

He then worked in Prof. Tobin Marks’s group at Northwestern University on solution processed amorphous oxide semiconductors for printable, thin-film electronics, before conducting research with Prof. Vivek Subramanian at UC Berkeley also in the area of printed electronics.

  • 11:30 am – Registration & light lunch (pizza & drinks)
  • Noon – Presentation & Questions/Answers
  • 1:00 pm – Adjourn
COST: $6, discount for IEEE Members, Students & Unemployed.

TITLE: Why STT-MRAM Will Soon Make A Major Market Impact


dong-il-moonSPEAKER:

Barry Hoberman, CEO and Chairman of the Board,

Spin Transfer Technologies, Inc.

Tuesday, March 21, 2017  11:30 AM – 1:00  pm
Texas Instruments (TI) Auditorium E-1
2900 Semiconductor Drive
Santa Clara, CA map

Cost $6, discount for IEEE Members, Students & Unemployed. Please register here.

 

ABSTRACT:

Thin film magnetics has been the heart of high density, high latency data storage for decades.  Semiconductor memory has filled the province of high throughput, low latency data storage.  Advances in semiconductor memory, particularly Flash, have enabled SSD’s to  encroach on the disk storage world.  Conversely, a technology from the historical disk drive domain of thin film magnetics will soon drive a new segment of semiconductor memory.  The magnetic tunnel junction, or MTJ, implemented with perpendicular magnetic orientation, and leveraging ‘spin transfer torque’ switching, will soon emerge to enable a significant new position in the semiconductor memory market.  New techniques for improving the switching characteristics of pMTJ devices will advance the state of the industry.

Image by A13ean Use licensed under the Creative Commons Attribution

SPEAKER BIOGRAPHY:

Barry Hoberman has served as CEO and Chairman of Spin Transfer Technologies since 2012.  He has over 35 years of management and engineering expertise in the semiconductor industry. Prior to his current role, he served as chief marketing officer at Crocus Technology, a semiconductor company.

Earlier, Hoberman was the founder and CEO of inSilicon, a leading semiconductor IP supplier, which was acquired by Synopsys in 2002. His leadership experience also includes CEO positions with Virtual Silicon and T-Zero Technologies. Earlier in his career, Hoberman held management positions at AMD and Monolithic Memories.

Hoberman holds B.S. degrees in Electrical Engineering and Biology from the Massachusetts Institute of Technology, and over 30 US patents.

AGENDA:

  • 11:30 am – Registration & light lunch (pizza & drinks)
  • Noon – Presentation & Questions/Answers
  • 1:00 pm – Adjourn
COST: $6, discount for IEEE Members, Students & Unemployed.

TITLE: Self Healing Nano-Electronics for Nano-Spacecraft in Deep Space Missions


dong-il-moonSPEAKER:

Dr. Dong-Il Moon, NASA Ames Research Center
Mountain View, CA

Tuesday, February 7, 2016  11:30 AM – 1:00  pm
Texas Instruments (TI) Auditorium E-1
2900 Semiconductor Drive
Santa Clara, CA map

Admission FREE ($5 donation requested). Please register here.

ABSTRACT:
Small satellites consisting of a set of integrated circuits (IC), i.e., nano-spacecraft, have been introduced recently to solve challenges such as propulsion cost and launch weight. The conventional spaceship takes 18,000 years from Earth to a nearest star, i.e., Alpha Centauri, but the spacecraft-on-a-chip technology dramatically reduces the travel time to 20 years due to its light weight and great energy efficiency. However, high risks of radiation induced damages and mission period over 20 years (longer than usual lifetime of IC) are considered as technology barriers. It is intrinsically impossible to avoid unexpected radiation exposure. The shielding metal adds significant weight, which nullifies the fundamental advantage of the nano-spacecraft. In this talk, self-healing process is introduced for sustainable space electronics. Degradation and recovery mechanisms for total ionizing dose, single event effect, hot carrier, and tunneling stress are discussed in silicon nanowire gate-all-around FETs. Dual contact pads of the gate allow current flow creating heat for on-chip annealing, which recovers interface states and bulk traps in the gate dielectric. The effect of the self-healing is examined for practical applications such as a logic transistor, high-speed DRAM, and non-volatile Flash memory. Therefore, the lifetime of devices can be extended, which opens an opportunity for nano-spacecraft sustainable for more than 20 years of deep space exploration. The technology will have an impact on terrestrial applications with critical requirements as well.

 

 

SPEAKER BIOGRAPHY:
Dong-Il Moon is a postdoctoral researcher at the Center for Nanotechnology at NASA Ames Research Center. He was previously a senior engineer of Device & Process Integration Technology Group at SK Hynix (2015). He received Ph.D. (2015) and M.S. (2010) in EE from KAIST, and B.S. (2008) in EECS from Kyungpook National University. His honors include the best Ph.D. thesis award in Department of EE at KAIST (2015), grand prize for thesis award from Lam Research Korea (2014), the best research student award in EE from KAIST twice (2012, 2014). His research includes fundamental and applied aspects of nano devices. He has explored the emerging nanoscale devices in layout, mask fabrication, wafer processing, simulation, and modeling. Especially, he led a research team responsible for developing the suspended silicon nanowire on a bulk silicon substrate, which is used as a basic building block for a nano-scale circuit. Based on the developed novel process, advanced MOSFETs such as a gate-all-around FET, a tri-gate FinFET, and an independently controlled double-gate FET were fabricated, which were utilized for various applications such as a logic transistor, a memory cell, and a biosensor. He has authored or coauthored one book chapter, 70 articles in peer-reviewed scientific journals, and 16 proceeding papers for international conferences.

 

AGENDA:

  • 11:30 am – Registration & light lunch (pizza & drinks)
  • Noon – Presentation & Questions/Answers
  • 1:00 pm – Adjourn
COST: FREE, but a $5 donation is requested to help cover the cost of lunch

 

Please register here.


 

TITLE: Toward realization of a silicon-based qubit system for quantum computing


malcolm-carroll-headshot
SPEAKER:
Dr. Malcolm Carroll, Principal Investigator for research on quantum computing at Sandia National Laboratories,
Albuquerque, NM

Thursday, Dec. 8th, 2016  11:30 AM – 1:00  pm
Texas Instruments (TI) Auditorium E-1
2900 Semiconductor Drive
Santa Clara, CA map

Admission FREE ($5 donation requested). Please register here.

 

ABSTRACT (extended here):
A qubit is a unit of quantum information—the fundamental currency of quantum computing, which is predicted to be hugely more efficient for solving problems that are challenging for traditional computers, such as breaking secret codes. This presentation will describe a path to development of a practical qubit design based on silicon CMOS processing technology. The qubit device is an electrostatic silicon quantum dot (QD) with an implanted donor. We demonstrate for the first time coherent two-axis control of a two-electron spin logical qubit that evolves under QD-donor exchange interaction as well as interaction with the donor nucleus, with decoherence as good as that of competing systems.

 

carroll-graphic

malcolm-carroll-pictures

 

SPEAKER BIOGRAPHY (extended here):
Malcolm Carroll is the Principal Investigator for research on silicon quantum computing at Sandia National Laboratories, including development of quantum dots, cryoelectronics and quantum error correction schemes for future quantum circuitry. In 2001 he received a Ph.D. in Electrical Engineering from Princeton University and joined Bell Labs/Lucent Technologies at Murray Hill, NJ. In 2003 and 2006 he became a senior and then principal member of the technical staff at Sandia National Laboratories. Dr. Carroll was a Fulbright Fellow and has been an author on over 50 peer reviewed articles and 3 patents. He co-founded and is an organizing committee member of the Silicon Quantum Computing Workshop series and is an external advisor for the Australian Centre for Quantum Computing Technology.

 

AGENDA:

  • 11:30 am – Registration & light lunch (pizza & drinks)
  • Noon – Presentation & Questions/Answers
  • 1:00 pm – Adjourn
COST: FREE, but a $5 donation is requested to help cover the cost of lunch

 

Please register here.


Please register for the fall symposium here.

Scroll down to see schedule of talks.

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2016-half-day-program


Commercializing Nanoscale Technology

Tuesday, October 25th, 2016  5:30 – 9:00  pm

Texas Instruments (TI) Auditorium E-1
2900 Semiconductor Drive
Santa Clara, CA map

Panel Speakers including CEOs and Co-founders

ieee_oct_talks_panel

Heat removal using carbon nanotubes Dr. Bara Cola CEO Carbice
Self assembling protein scaffolds Prof. Daniel Cox CEO Protein Architects
Biological transistors to solve cancer Dr. Ben Wang CEO Chimera Bioengineering
Miniature sensors, microfluidics, diagnostics Dr. Ned Saleh Co-Founder and COO Plasmotica
Nanotech solutions for semiconductor manufacturing Vic Kley CEO General Nanotechnology LLC

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 Please register here.

Event includes a Discussion Panel, Networking, Job Table

 

 


TITLE: Metrology in Nanotechnology

SPEAKER:
Dr. Min Yang, Director of Applications Development at Bruker Nano Surfaces

min-yang-headshot

Tuesday, October 18th, 2016  11:30 AM – 1:00  pm

Texas Instruments (TI) Auditorium E-1
2900 Semiconductor Drive
Santa Clara, CA map

Admission FREE ($5 donation requested). Please register here.

ABSTRACT:

We are now in a very exciting period of time when many new and disruptive technologies emerge across a wide range of industries, making the existing technologies obsolete faster than anyone could anticipate. The new products with emerging technologies are generally smaller, lighter, stronger, more reliable and cheaper. To achieve all these, process control has becoming more important than ever, which gives good opportunities for various metrology tools to be incorporated into the advanced manufacturing processes. This leads to new challenges to integrate the metrology tools into the manufacturing tools. In this talk, I will review and compare several metrology tools and their applications in nanotechnology, and discuss about some of the challenges in integrating the tools into the manufacturing process.

min-yang-graphic

SPEAKER BIOGRAPHY:

Dr. Min Yang joined Bruker Nano Surfaces as Director of Applications Development, responsible for developing new applications for tribology, optical and stylus metrology, and optical coordinate measurement. Min has over 20 years of experience in tribology, metrology and failure analysis, mostly in the data storage business in Silicon Valley. She started her career as a tribology integration engineer for head/disk interface designs and held a number of positions at IBM and Western Digital in tribology and failure analysis. Prior joining Bruker, Min was an Engineering Director at Western Digital, responsible for the development of tribology and failure analysis testing on a wide variety of instruments including, SEM/EDX, AFM, FIB, TOF-SIMS, FTIR, Raman, optical analysis tools, and test chambers. Min holds a BSEE from Beijing University of Technology, a Masters in Materials Science from Beijing Aeronautical Materials Institute, and both a Masters in Mechanical Engineering and a PhD in System Engineering from UC San Diego.

AGENDA:

  • 11:30 am – Registration & light lunch (pizza & drinks)
  • Noon – Presentation & Questions/Answers
  • 1:00 pm – Adjourn
COST: FREE, but a $5 donation is requested to help cover the cost of lunch

Please register here.

Also, visit our Meetup Group.


TITLE: Electronic, Thermal, and Unconventional Applications of 1D and 2D Materials

SPEAKER:
Prof. Eric Pop, Stanford University, Electrical Engineering

EricPop_Headshot

Tuesday, September 20th, 2016  11:30 AM – 1:00  pm

Texas Instruments (TI) Auditorium E-1
2900 Semiconductor Drive
Santa Clara, CA map

Admission FREE ($5 donation requested). Please register here.

ABSTRACT:

One-dimensional (1D) materials like carbon nanotubes (CNTs) and two-dimensional (2D) materials like graphene have potential applications in low-power electronics and energy-conversion systems. These are also rich domains for fundamental discoveries as well as technological advances. This talk will present recent highlights from our research on CNTs, graphene, and MoS2. As an example, we used CNTs to enable the most energy-efficient phase-change memory (PCM) devices to date. We have also studied graphene from basic transport measurements, to the recent wafer-scale demonstration of analog dot product nanofunctions. We are presently evaluating the unusual thermal and thermoelectric properties of other 2D materials (like MoS2) which could lead to unconventional applications in energy harvesters and thermal circuits. Our studies ultimately reveal fundamental limits and new applications that could be achieved through the co-design and heterogeneous integration of 1D and 2D nanomaterials. For more info please visit http://poplab.stanford.edu.

EricPop_Graphic

SPEAKER BIOGRAPHY:

Eric Pop (epop@stanford.edu) is an Associate Professor of Electrical Engineering (EE) at Stanford, where he leads the SystemX Heterogeneous Integration Focus Area. He was previously on the faculty of the University of Illinois Urbana- Champaign (2007-13) and worked at Intel (2005-07). His research interests are at the intersection of electronics, nanomaterials, and energy. He received his PhD in EE from Stanford (2005) and three degrees from MIT (MEng and BS in EE, BS in Physics). His honors include the 2010 PECASE from the White House, and Young Investigator Awards from the ONR, NSF CAREER, AFOSR, and DARPA. He is an IEEE Senior member, he served as the General Chair of the Device Research Conference (DRC), and on program committees of the VLSI, IRPS, MRS, IEDM, and APS conferences. In a past life, he was a DJ at KZSU 90.1 from 2001-04.

AGENDA:

  • 11:30 am – Registration & light lunch (pizza & drinks)
  • Noon – Presentation & Questions/Answers
  • 1:00 pm – Adjourn
COST: FREE, but a $5 donation is requested to help cover the cost of lunch

Please register here.

Also, visit our Meetup Group.


TITLE: There’s pleProf. Tsu-Jae King Liunty of room at the Bottom- and at the Top

SPEAKER:
Prof. Tsu-Jae King Liu
Department of Electrical Engineering and Computer Sciences
University of California, Berkeley

Tuesday, August 16th, 2016  11:30 AM – 1:00  pm
Texas Instruments (TI) Auditorium E-1
2900 Semiconductor Drive
Santa Clara, CA map

Admission FREE ($5 donation requested). Please register here.

ABSTRACT:

The virtuous cycle of integrated-circuit (IC) technology advancement has been sustained for over 50 years, resulting in the proliferation of information and communication technology with dramatic economic and social impact. Industry experts predict that the pace of increasing transistor density will slow down dramatically within the next 5 years, however, due to fundamental limits of the conventional photolithographic patterningprocess. Scaling of IC feature sizes beyond the resolution limit of lithography has been enabled by multiple-patterning techniques, but at significant incremental cost. In the first part of this seminar, I will describe a more cost-efficient approach for defining sub-lithographic features, to help extend the era of Moore’s Law.

TsuJaeLu_Device_Schematic             TsuJaeLu_Device_SEM

 
Beyond Moore’s Law,the proliferation of mobile electronic devices and the emergence of applications such as wireless sensor networks and the Internet of Things have brought energy consumption to the fore of challenges for future information-processing devices. The energy efficiency of a digital logic integrated circuit is fundamentally limited by non-zero transistor off-state leakage current. Mechanical switches have zero leakage current and potentially can overcome this fundamental limit. In the second part of this seminar, I will describe recent progress toward realizing the promise of ultra-low-power mechanical computing.

SPEAKER BIOGRAPHY:
Tsu-Jae King Liu received the B.S., M.S., and Ph.D. degrees in Electrical Engineering from Stanford University. From 1992 to 1996 she was a Member of Research Staff at the Xerox Palo Alto Research Center (Palo Alto, CA). In August 1996 she joined the faculty of the University of California, Berkeley, where she currently holds the TSMC Distinguished Professorship in Microelectronics in the Department of Electrical Engineering and Computer Sciences and serves as Associate Dean for Academic Planning and Development in the College of Engineering.

Dr. Liu’s research awards include the DARPA Significant Technical Achievement Award (2000) for development of the FinFET, the IEEE Kiyo Tomiyasu Award (2010) for contributions to nanoscale MOS transistors, memory devices, and MEMs devices, the Intel Outstanding Researcher in Nanotechnology Award (2012), and the Semiconductor Industry Association Outstanding Research Award (2014). She has authored or co-authored close to 500 publications and holds over 90 U.S. patents, and is a Fellow of the IEEE. Her research activities are presently in advanced materials, process technology and devices for energy-efficient electronics.

AGENDA:

  • 11:30 am – Registration & light lunch (pizza & drinks)
  • Noon – Presentation & Questions/Answers
  • 1:00 pm – Adjourn
COST: FREE, but a $5 donation is requested to help cover the cost of lunch

Please register here.

Also, visit our Meetup Group.