SF Bay Area Nanotechnology Council

IEEE

August 21st, 2018: Real Limits to Nanoelectronics: Interconnects and Contacts

Real Limits to Nanoelectronics: Interconnects and Contacts

Registration: HERE

Professor Krishna Saraswat

Department of Electrical Engineering, Stanford University

Date & Time: Tuesday, August 21, 2018
                             11:30AM – Networking & Pizza
                             Noon-1PM – Seminar
Location: EAG Laboratories – 810 Kifer Road, Sunnyvale
Cost: $6; discounts for IEEE Members, Students & Unemployed

ABSTRACT

Modern electronics has advanced at a tremendous pace over the course of the last half century primarily due to enhanced performance by scaling MOS transistors. As device scaling continues to nanoscale, parasitic contact resistance is beginning to limit the device performance. While novel structures and materials continue to enhance the transistor performance, the opposite is true for the interconnects that link these transistors resulting in excessive power dissipation, insufficient communication bandwidth, and signal latency. This talk will address effects of scaling on the performance of conventional contacts and interconnects, and explore alternate contact forming techniques and interconnect schemes including carbon nanotubes (CNT), graphene, optical interconnect, 3-D structures and heterogeneous integration of these technologies on the silicon platform.

SPEAKER BIOGRAPHY

Prof. Krishna Saraswat is the Rickey/Nielsen Chair Professor in the School of Engineering, Professor of Electrical Engineering and by courtesy Professor of Materials Science & Engineering at Stanford University. He received Ph.D. from Stanford University and B.E. from BITS, Pilani. His research interests are in new and innovative materials, structures, and process technology of semiconductor devices and metal and optical interconnects for nanoelectronics, and high efficiency and low cost solar cells. Prof. Saraswat has supervised more than 90 doctoral students, 30 post doctoral scholars and has authored or co-authored 18 patents and over 800 technical papers, of which 10 have received Best Paper Award. He is a Life Fellow of the IEEE. He received the Thomas Callinan Award from The Electrochemical Society in 2000 for his contributions to the dielectric science and technology, the 2004 IEEE Andrew Grove Award for seminal contributions to silicon process technology, Inventor Recognition Award from MARCO/FCRP in 2007, the Technovisionary Award from the India Semiconductor Association in 2007, BITS Pilani Distinguished Alumnus Awards in 2012 and the Semiconductor Industry Association (SIA) Researcher of the Year Award in 2012. He is listed by ISI as one of the Highly Cited Authors in his field.

 

 

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