Tuesday, September 15, 2015
Noon – 1 pm
Texas Instruments (TI) Auditorium E-1
2900 Semiconductor Drive
Santa Clara, CA
SPEAKER: Dr. Ethan C. Ahn, Dept of Electrical Engineering, Stanford Nanoelectronics Lab
With the advent of so-called ‘big data’ era and the increasing need for greater storage capacity in various mobile and wearable devices, it is becoming more important to explore a new storage-class memory technology. As illustrated in recent research articles and papers, significant progress on emerging non-volatile memory (NVM) devices such as spin-transfer-torque magnetic random access memory (STT-MRAM), resistive or metal-oxide RAM (RRAM), or phase-change memory (PCM), made it possible to replace the mainstream NVM (NAND Flash) and even reach certain on-chip memory requirements (e.g., L2/L3 SRAM cache). This is important, as the energy efficiency of computing circuits/systems has been increasingly limited by the memory and storage devices. In this talk, a frontier research on the near- and long- term potential of emerging nanoscale memory devices and architectures will be discussed to replace ultimately scaled CMOS memory device technologies. The emerging 1TnR (one-transistor-n-resistors) array architecture with carbon nanotube field-effect transistor as one-dimensional selection device and thus reduced sneak leakage is demonstrated as a cost-effective and 3D-stackable solution. The integrated bipolar RRAM device, for example, exhibits self-compliance characteristics with high endurance and fast switching speed. It is pointed out that the carbon nanotube electrode brings the (lithography-free) critical dimension of the memory device down to a single-digit-nanometer. The novel thermal engineering technique for low-power NVM applications is also introduced using a monolayer graphene as an interfacial thermal barrier. The programming (RESET) current of the graphene-inserted PCM device is reduced by about 40% due to an improved thermal efficiency. The status, key challenges, and promising applications of the RRAM, PCM, and STT-MRAM technologies will be briefly discussed in the talk.
Dr. Ahn received the Ph.D. in Electrical Engineering (EE) at Stanford University in 2015, working under the supervision of Professor H.-S. Philip Wong. He joined Stanford University in 2010, after a 3-year research career on Spintronic devices (STT-MRAM) with the Korea Institute of Science and Technology (KIST) in Seoul, Korea. While at KIST, he initiated the collaborative research program with Michigan State University to study spin-dependent transports in magnetic multilayers and spinvalves. He received the B.S. and M.S. degrees in EE from the Korean Advanced Institute of Science and Technology (KAIST) in Daejeon, Korea. He is the author of over 10 peer-reviewed research journal papers in electrical engineering and applied physics, over 20 premier international conference papers, and one book chapter of Emerging Nanoelectronic Devices (ed. A. Chen, John Wiley & Sons, Ltd, Jan. 2015). His primary research interests include emerging non-volatile memory devices and architectures (including Metal-oxide RAM and Phase-Change Memory), beyond CMOS electronics (utilizing Carbon Nano-materials such as Carbon Nanotube and graphene), and various spintronic devices (including STT-MRAM and Spin-FET). Dr. Ahn has been the recipient of numerous awards and honors, including John Bardeen Student Research Award for Excellence in Nanodevice Research (2014), Best Summer Research Intern Award by T.-C. Chen at IBM T. J. Watson (2013), and GE Scholarships (2004).
- 11:30 am – Registration & light lunch (pizza & drinks)
- Noon – Presentation & Questions/Answers
- 1:00 pm – Adjourn
Please RSVP here to make sure we have enough lunch.