The Executive Committee leads the activities of the IEEE San Francisco Bay Area Nanotechnology Council.
We look forward to meeting you in person at an upcoming event!
Links below connect to additional biographical information or contact information for the committee members.
Geetha Dholakia, Chair – Dr. Dholakia’s research interests are at the interface of Physics, Materials Science and Electrical Engineering. She studies electronic transport at the nanoscale in nanomaterials and soft materials, researching the application of multifunctional materials such as nanowires, nanoscale films and organic films to organic electronic devices and photovoltaic systems. She has extensive experience in scanning probe microscopy and its instrumentation and has worked to miniaturize instruments for NASA on board rover missions. She has been associated with IEEE SFBA Nanotechnology Council since 2008. During this time she has organized and co-chaired two conferences – Nanotech Enabled Energy Generation & Management in 2009 and Nanotechnology Consumer Applications in 2011. She received a PhD in Physics from the Indian Institute of Science, Bangalore, India and Masters in Physics from the Indian Institute of Technology, Madras, India.
Jack Berg – Mr. Berg is a co-founder and Chief Technologist of American Semiconductor, where he has been developing and producing radiation-hard integrated circuits. Before joining American Semiconductor, he co-founded Transfer Devices, a spin-out commercializing lithography technology developed in Professor Fabian Pease’s laboratory. Prior to Transfer Devices, Mr. Berg was the General Manager of Cypress Semiconductor’s Programmable Logic Business Unit,from 1998 to 2002. Before Cypress, he was Vice President of Technology Development at Zilog, where he directed Z8 product design, and led CMOS and embedded non-volatile memory process development.
Mr. Berg earned a Masters of Science degree from Stanford University, where he was a Sloan Fellow, and a Bachelor of Science degree from the Massachusetts Institute of Technology. Jack is a co-founder of the IEEE San Francisco Bay Area Nanotechnology Council, and is an Executive Committee Member of IEEE’s Western United States Section. He is a technical and commercial reviewer at the National Science Foundation, and is on the Board of several privately held Bay Area firms.
Dhaval Brahmbhatt – Mr. Brahmbhatt brings over 30 years of experience in the Silicon Valley as Engineer, Adjunct Faculty, Technologist, entrepreneur businessman, community leader, and as a Senior Executive. He has founded high-tech companies and has also provided guidance to entrepreneurs. He is a creative technologist with 11 US patents and has provided services as an IP Expert Witness. Mr. Brahmbhatt has reviewed SBIR/STTR grant applications for various agencies of the United States Government in subjects ranging from Nanotechnology, Advanced Semiconductors, MEMS/NEMS, to Communications, sensors, etc. Mr. Brahmbhatt is a registered Language Interpreter with California Judicial Council for 6 south Asian languages (from India) and one language from Fiji.
Mr. Brahmbhatt founded the IEEE SF Bay Area Nanotechnology Council and is its past Chairman. Mr. Brahmbhatt has taught Nanotechnology courses at SPIE annual conferences, Santa Clara University Graduate School of Engineering and at the Ohlone College. He was placed on the Nanotechnology Advisory Board of Foothill College and on the Committee to Advance Nanoscience Education at SRI. Mr. Brahmbhatt was a member of the Blue Ribbon Task Force on Nanotechnology for the State of California and worked on its Education Sub-committee. He is a Senior member of the IEEE and is also involved with the IEEE Vehicle Technology Society. He has been recognized numerous times by the IEEE with citations and awards. Mr. Brahmbhatt is the former President and Board Member of the prestigious Silicon Valley Engineering Council.
He is currently President & CEO of PHYchip Corporation, a company he founded in 2002. This company works in renewable energy, IP expert witness work, and government contracts. He has earned a graduate degree in Physics from India and a MS Electrical Engineering degree from the University of Cincinnati. He is a certified energy efficiency engineer and a green building professional.
Paul Brunemeier – Dr. Brunemeier is a nanotechnology and semiconductor scale-up artist and has developed and scaled materials and device processes and equipment (LEDs, FETs, MEMS, nano, and CMOS silicon) throughout a career spanning nearly 30 years. He currently is Sr. Director of Engineering for Arcanum Alloy Design, where he is developing and executing the company’s plan for pilot manufacturing. Prior to this he served as Sr. Director of Engineering for Amprius, scaling up their silicon nanowire lithium-ion battery technology. During his tenure there he improved material yields from zero to production-worthy levels and designed equipment and processes that increased throughput by a factor of 400x. Prior to this, he transferred and scaled processes and equipment for opto-thyristors from the Ioffe Institute in St. Petersburg, Russia, and developed a captive foundry for GaAs epitaxial wafers for Watkins-Johnson Company. Dr. Brunemeier has about 20 publications and is primary inventor on five patents, four of which entered production. Additionally, he holds a physics PhD from University of Illinois, and conducted his thesis research in semiconductor quantum-well lasers in the laboratory of Nick Holonyak, Jr., the inventor of the LED. Dr. Brunemeier also earned a physics BS from University of California at Davis, with a concentration in physics of materials.
Ira Feldman, Secretary – Mr. Feldman is the principal consultant at Feldman Engineering Corp., where he manages and develops unique high technology solutions and business strategies. As a successful executive, he has proven his leadership ability to resolve product management and engineering challenges within organizations as well as with their supply chain and customers. Mr. Feldman’s broad knowledge and management experience with high volume manufacturing of complex technology products is the result of his extensive expertise in the semiconductor test and computer test industries. As Vice President of Business Development for Microfabrica, he identified and successfully brought to market many new applications for their EFAB technology (which is a breakthrough platform that enables the creation of sub-millimeter, 3D, fully-assembled micro-machines and precision parts of unprecedented scale and performance). Previously, at the probe card manufacturer NanoNexus, he was the Director of Products and Applications and the Director of Design Engineering. He managed a global team of engineers at Agilent Technologies (now Verigy/Advantest) that integrated Automatic Test Equipment (ATE) into end customers’ high volume manufacturing facilities prior to that. At Hewlett-Packard, at the star of his career, he drove the successful manufacturing introduction and ramp up of several generations of high-end mini-computers. He earned both a BS in Engineering and a Master of Engineering degree from Harvey Mudd College. And he publishes his “High Technology Business Development” blog which often covers nanotechnology, MEMS, semiconductor, and test topics.
Jessica Koehne - Dr. Koehne has worked for the NASA Ames Center for Nanotechnology since 2001. Her expertise is in the development of ultrasensitive nanomaterials based biosensors for health diagnostics. Dr. Koehne has published over 20 articles in peer-reviewed journals and given 16 presentations at scientific conferences including 7 invited talks. She has received 8 awards from NASA including the 2011 NASA Ames Honor Award in the category of scientist. In 2012, Dr. Koehne received a Presidential Early Career Award for Scientists and Engineers (PECASE). In addition to nanotechnology research, she is an advocate for student education in STEM fields, especially to underrepresented students, by serving on advisory boards of a NASA University Research Center (URC) and two NASA Science and Technology Institutes (NSTI). Over the past 4 years, she has mentored 23 students in nano-biosensor development and research.
Nick Massetti, Vice-Chair - Mr. Massetti has over 40 years of industry experience spanning multiple applications of integrated circuit device and fabrication technology. He is currently Sr. Technology and IP Coordinator for image sensor manufacturer OmniVision Technologies. Prior to that he directed technology related assessments of intellectual property for IPValue Management. He mined and evaluated the patent portfolios of Fortune 500 high-tech companies. He previously served as Senior Director, VLSI Manufacturing Technology, for HDD industry leader Seagate Technology where he ensured mass market commercialization of state-of-the art IC fabrication technology. Prior to that, he was Director of Technology Development & Quality Systems at Texas Instruments. There he developed and applied high speed analog BiCMOS manufacturing technologies to products used in high capacity storage systems, wireless communication components, and PC processor interfaces. Earlier in his career he developed CMOS logic and non-volatile memory technologies, and managed pilot fabrication lines at NCR Microelectronics and Philips Semiconductors. In his initial career assignment at Hughes Aircraft he fabricated a space qualified image sensor subsequently used for Earth Resources imaging on the Landsat IV Satellite. He has been active in promoting nanotechnology by organizing forums and speaking on the subject. He has published related on-line articles. Since 2005 he has held multiple Chapter officer positions for the San Francisco Bay Area IEEE Nanotechnology Council Chapter. As an NSF peer reviewer he continues to support investments in small high tech businesses. Mr. Massetti holds a Master of Science degree in Applied Solid State Physics from the University of California, San Diego. He also earned his Bachelor of Science degree in Physics at St. Mary’s College of California.
K R S Murthy – Dr. Murthy is a polymath inventor and expert in nano, solar, big data, and video games. He holds the track record for the fastest growing private company in the USA. He grew a variety of companies by both organically and inorganically, one of them from $60M to $550M in revenue only one year and a valuation to $3.5B. He has served on the board of directors the of IEEE and the boards of six IEEE societies. Dr. Murthy is an expert in mergers and acquisitions (M&A) and corporate governance.
Jeongwon Park – Dr. Park is senior research scientist in the Advanced Technologies Group, Office of the CTO Group, at Applied Materials, USA. He is an adjunct professor in the department of electrical engineering at Santa Clara University. He received a PhD from the University of California, San Diego in Materials Science and Engineering in 2008. His expertise is in nano-materials including CNT and graphene, nano-electronics, III-V semiconductor and Silicon Integrated Circuit processing coupled with a strong background in design and test. In addition to the industrial affiliations, he is currently involved with a close collaboration program with Stanford EE faculty members (Profs. Saraswat, Nishi, Phillip Wong, etc), MIT and UC Berkeley though his position at Applied Materials. His teaching efforts at Santa Clara include graduate level coursework on: “Fundamentals of Semiconductor Physics”, “Nanoelectronics”, “Nanotechnology”, “Nanomaterials”, etc in the Electrical Engineering Department at Santa Clara University. During his PhD, he focused on nanoelectronics with carbon nanotubes and organic field effect transistors including fabrication within a clean room, experience with CMOS, MEMS, packaging, device processing/measurements, simulations and modeling tools. These supplemental areas of focus and his continued interest and study of epitaxial Si, SiGe, III-V cleaning, Carbon Nanotube, Graphene, and similar materials have been on-going in parallel with his professional career. He has been a guest researcher at NASA Ames Research Center, Lawrence Berkeley National Labs(LBNL), and Sun Microsystems, in addition to his work at UCSD, Hanyang University, Institute for Advanced Engineering, and Seoul National University in Korea. He has published more than twenty papers.
John Paul Strachan, Treasurer – Dr. Strachan is a researcher at Hewlett-Packard Labs. He received his BS in physics and PhD in applied physics from Massachusetts Institute of Technology in 2001 and Stanford University in 2007, respectively. He has published 24 peer-reviewed papers and holds 6 patents, with more than 30 pending. He currently develops next generation memories and computational devices at HP. Previously, he has researched nanomagnetic devices for non-volatile memory, and nutrient sensors for precision agriculture with Solum, Inc, which he helped co-found. His interests include nanoelectronics, sensors, novel computational schemes, and generally finding new ways to understand and exploit material, structural, and electronic properties at the nanoscale.
Kris Verma - Dr. Verma is a veteran of the Semiconductor Industry with over 37 years experience in Semiconductor Devices, Fabrication, Factories buildings, R/D, Reliability plus 5 years in the Hard Disk Drive Industry , all in Silicon Valley, California. His expertise resides in CMOS processes, Devices, Wafer Manufacturing, VLSI CHIPS for HDD and R/D projects management in High Tech Industry. Presently, he is engaged as a Sr. Faculty member at California Polytechnic Institute training engineers through courses including: Solar Energy’s Opportunities and Challenges, Nano-Technology, and Smart Power Grid. He is also Program Director for CalPT’s Symposium on Solar Energy. He was awarded an IEEE Millennium medal winner in 2000 for his contributions including 20 published papers and chairing numerous IEEE meetings and conferences. He is also an Emeritus Chairperson of the IEEE SFBA Nanotechnology Council. In addition, he is also involved as an IEEE officer for Photovoltaic chapter start-up and SVEC Board Member. Dr. Verma was awarded an ISQED fellowship and Best Engineer Award from IEEE Santa Clara valley Section in 2008 and 2010 respectively. He earned his PhD in EE from University of Utah, Salt Lake City and MBA from Portland University, Oregon.
Anshul Vyas, Senior Student Liaison – Mr. Vyas completed his BS from University of Mumbai (First Class Honors), his MS from Santa Clara University (Distinction) and is now working towards his Ph.D. His research interests include Fabrication and Characterization of Copper-Vias, Carbon Nanotube Interconnects. He established the IEEE EDS Santa Clara University chapter and served as the founding chair. As a member of IEEE Nanotechnology Executive Committee he leads and drives student related events.
Jianhua (Joshua) Yang – Dr. Yang is Principal Research Scientist at HP Labs, leading the ReRAM (Memristor) device study effort. His current research interest is Nanoelectronics and Nanoionics, especially for memory and computing applications, where he authored and co-authored over 100 papers in academic journals and international conferences, and holds 15 granted and over 60 pending US Patents. In the last 3 years, he has been invited to international conferences or universities to give over 20 keynote speeches, invited talks, or seminars. He recently guest-edited two journal special issues on Non-volatile Memory technologies for Nanotechnology and Applied Physics A, respectively. He also serves as a co-editor of Applied Physics A. He obtained his PhD from the University of Wisconsin – Madison in Material Science Program in 2006 and joined HP at that time.
Chairpersons Emeritus: Dhaval Brahmbhatt, Jack Berg, Allen Amaro, Nitin Parekh