SF Bay Area Nanotechnology Council

IEEE

Executive Committee

The Executive Committee leads the activities of the IEEE San Francisco Bay Area Nanotechnology Council.

We look forward to meeting you in person at an upcoming event!

Links below connect to additional biographical information or contact information for the committee members.

Glenn Friedman 250x250Glenn Friedman, Chair

Glenn Friedman, 2018 Chair, previously served as Chair in 2015 and 2017.

He currently serves as 2018 Vice Chair of the IEEE Santa Clara Valley Section. In that capacity, he distilled many of SFBA Nano’s successful practices into training sessions which have been incorporated into IEEE SFBA Officers Training and shared with all of IEEE Region 6.

Glenn Friedman is currently the principal technologist and analyst at Gxtec Consulting, where he has created strategies for novel device manufacturing, consulted on materials, processing, foundry relationships, and startup operations.

He has completed 100 technical and commercial reviews of SBIR/STTR proposals for National Science Foundation in the areas of: new manufacturing technologies, electronics manufacturing, semiconductor manufacturing; semiconductors, emerging memory devices, integrated circuits, photovoltaics, batteries, MEMS integrated systems, optical & electronic materials, hi-tech medical applications, biomedical nanotechnology, and nano-instrumentation.

Glenn is a veteran of the silicon and compound semiconductor industries. He has held engineering and management positions in wafer fabs and in foundry services providers to the fabless semiconductor sector.

While holding wafer fab manager and engineering manager positions he has achieved radical yield and productivity improvements in both silicon and compound semiconductor wafer fabs.

Glenn Friedman’s commercial research and development activities have included phase change memories, interlevel dielectrics, and multilevel interconnects. His academic research focused on high temperature superconducting thin films, and phase change memory effects.

Glenn Friedman earned a Master of Science in Electrical Engineering – Applied Physics from the University of California at San Diego with thesis research into high temperature superconducting thin films and substrate barrier layers; while supervising the design and construction of two thin films research laboratories. He also earned a Master of Science in Physics at North Carolina State University where he performed thesis research into high-field transport and discovered phase change Ovonic switching effects in CdTe thin films. He holds a Bachelor of Science in Physics from North Carolina State University.

 

Vasuda headshot

Vasuda Bhatia, Vice Chair

Dr. Bhatia is a professor at Amity Institute of Renewable and Alternative Energy and Amity Institute of Advanced Research and Studies, Amity University, India. She received her B.Tech. (Bachelors of Technology) in Materials and Metallurgical Engineering from Indian Institute of Technology (IIT) Kanpur, India in 1995, MS in Materials Science from the University of Cincinnati in 1997 and the Ph.D. in Electrical Engineering from Texas A&M University in 2001. She was research scientist at Stellar Micro Devices, Austin, Texas; visiting faculty at IIT Kanpur, India and research associate at Jawaharlal Nehru Centre for Advanced Scientific Research, Bangalore, India. Her research interests include synthesis, characterization and device applications of nanomaterials; materials for renewable energy applications; field emission devices and materials and development of sensors and sensing devices for bio, chemical and gas applications.

 

Valls intel gardner

Don GardnerTreasurer

Donald Gardner is an IEEE Fellow and a Principal Engineer at Intel. He received his Ph.D. in Electrical Engineering from Stanford University. Donald is the inventor or co-inventor of 96 granted U.S. patents including for high-frequency voltage converters, embedded and electrochemical capacitors, and inductors using magnetic materials. He has published 160+ papers that have been cited by over 4,400 authors (h-index = 32). He has received five Best Paper and Poster awards and Intel’s highest technical award “For Fundamentally Changing Platform Power Delivery with Integrated Voltage Regulators and Magnetic Inductors on CMOS”. In addition, an award for the “World’s First Integrated Voltage Regulator” was bestowed for the idea of creating high-frequency integrated voltage regulators which was implemented by a team of brilliant designers in the “Haswell” fourth-generation Intel microprocessors which resulted in a 50~100% laptop battery life increase. He also invented embedded MIM capacitors that are in third and fourth generation Intel microprocessors. Don also developed integrated inductors with magnetic material that have the highest inductance density known. He invented new electrochemical capacitors for energy storage suitable for IoTs. He also conceived reflowed copper technology and used it to fabricate the first working chip with copper-based interconnections and also invented an Al alloy/Ti metallization for interconnections that was widely used by most microchip manufacturers. His current interests include energy storage devices, power delivery technology for future microprocessors, magnetic materials for inductors, new materials integration and nanostructure design.

 

Roland Lee, Secretary

Dr. Roland Lee is a nanotechnology expert with over fifteen years of experience in developing nanomaterial-enabled products.  He received his BSE and PhD in materials science and engineering at the University of Pennsylvania, after which he post-doc’ed at ONERA (the French National Aerospace Office), whereupon he returned to the United States to work at Carbon Nanotechnologies, Inc., the carbon nanotube company founded by the late Dr. Richard Smalley, winner of the 1996 Nobel Prize in Chemistry.  Since then, Roland has worked for a number of start-up companies focused on commercializing graphene- or carbon nanotube- enabled products, the most recent being Graphene Technologies, Inc., where he served as the Vice-President of Research and Development.  Roland is currently working as an independant consultant in nanotechnology, where his work is focused on the synthesis, processing, and characterization of nanomaterials.

 

 

20150604_Lincoln

Lincoln Bourne, Publicity

Lincoln is a Senior Scientist/Engineer at IBM. He helped launch Linear Tape Open, a new platform for magnetic data storage, with revenues now exceeding $1 Billion per year. His current role is to move new materials and processes into mass production. Before IBM, Lincoln joined two early-stage startups seeking to commercialize novel materials, and helped each to achieve a successful IPO – Superconductor Technologies and Conductus. Lincoln has a PhD in Physics from UC Berkeley, where he was a National Science Foundation Fellow. He led the team that found the mechanism of high-temperature superconductivity to be fundamentally different from the phonon-mediated electron pairing of all previous superconductors, a result described by Physics Today as “A tour de force, experimentally”.

 

 

BOARD MEMBERS:

K R S Murthy

Dr. Murthy is a polymath inventor and expert in nano, solar, big data, and video games. He holds the track record for the fastest growing private company in the USA.He grew a variety of companies by both organically and inorganically, one of them from $60M to $550M in revenue only one year and a valuation to $3.5B.

He has served on the board of directors the of IEEE and the boards of six IEEE societies. Dr. Murthy is an expert in mergers and acquisitions (M&A) and corporate governance.

 

Ranjeet Pancholy– Dr. Pancholy is a Semiconductor Technology Expert with over 30 years of Advanced Technology Research and Development, Fabless Manufacturing, and Cost Optimization experiences for ASIC/SOC, Nanotechnology and Renewable Energy fields. He is currently a Consultant for Global clients for Industry, Operations, Management and Manufacturing of Semiconductor and Renewable Energy Products. Previously, Dr. Pancholy worked at large Multinational Semiconductor companies like Qualcomm Technologies, Seagate Technology, Cypress Semiconductors, Rockwell International and Hughes Aircraft Company in Research, Engineering and Management Capacities managing over $4B per year production of ASICs/ SOCs/MEMs and mobile chip sets. Dr. Pancholy has 5 US and International Patents and over 30 Publications in International Journals and Conferences. He has been an editor of IEEE Transactions on Electron Devices, Consultant and United Nations UNDP Advisor to Government of India for SCL Chandigarh Fab, Executive Committee member Conference Organizer and Chairman of several IEEE conferences on Electron Devices, Nanotechnology, Reliability Physics and Nuclear Radiation Effects. He received his PhD. Degree in Electrical Engineering from University of New Mexico, Albuquerque, NM, a MSEE from Oklahoma State University, Stillwater Oklahoma and M.Sc. and B.Sc. Physics degrees from the Birla Institute of Technology & Science, Pilani, India. He is member of executive Committee of San Francisco Bay Area Nanotechnology Council and currently involved with new advanced micro wind and micro power renewable energy devices.

 

John Paul Strachan – Dr. Strachan is a researcher at Hewlett-Packard Labs. He received his BS in physics and PhD in applied physics from Massachusetts Institute of Technology in 2001 and Stanford University in 2007, respectively. He has published 24 peer-reviewed papers and holds 6 patents, with more than 30 pending. He currently develops next generation memories and computational devices at HP. Previously, he has researched nanomagnetic devices for non-volatile memory, and nutrient sensors for precision agriculture with Solum, Inc, which he helped co-found. His interests include nanoelectronics, sensors, novel computational schemes, and generally finding new ways to understand and exploit material, structural, and electronic properties at the nanoscale.

Kris Verma – Dr. Verma is a veteran of the Semiconductor Industry with over 37 years experience in Semiconductor Devices, Fabrication, Factories buildings, R/D, Reliability plus 5 years in the Hard Disk Drive Industry , all in Silicon Valley, California. His expertise resides in CMOS processes, Devices, Wafer Manufacturing, VLSI CHIPS for HDD and R/D projects management in High Tech Industry. Presently, he is engaged as a Sr. Faculty member at California Polytechnic Institute training engineers through courses including: Solar Energy’s Opportunities and Challenges, Nano-Technology, and Smart Power Grid. He is also Program Director for CalPT’s Symposium on Solar Energy. He was awarded an IEEE Millennium medal winner in 2000 for his contributions including 20 published papers and chairing numerous IEEE meetings and conferences. He is also an Emeritus Chairperson of the IEEE SFBA Nanotechnology Council. In addition, he is also involved as an IEEE officer for Photovoltaic chapter start-up and SVEC Board Member. Dr. Verma was awarded an ISQED fellowship and Best Engineer Award from IEEE Santa Clara valley Section in 2008 and 2010 respectively. He earned his PhD in EE from University of Utah, Salt Lake City and MBA from Portland University, Oregon.

 

VOLUNTEERS:

Catherine Tran, Webmaster

 

CHAIRPERSONS EMERITUS: Paul Brunemeier, Glenn Friedman, Nick Massetti, Dhaval Brahmbhatt, Jack Berg, Allen Amaro, Nitin Parekh, Geetha Dholakia

 

ADVISORS

Nick Massetti – Mr. Massetti has over 40 years of industry experience spanning multiple applications of integrated circuit device and fabrication technology. He has recently retired from the position of Sr. Technology and IP Coordinator for image sensor manufacturer OmniVision Technologies. Prior to that he directed technology related assessments of intellectual property for IPValue Management. He mined and evaluated the patent portfolios of Fortune 500 high-tech companies. He previously served as Senior Director, VLSI Manufacturing Technology, for HDD industry leader Seagate Technology where he ensured mass market commercialization of state-of-the art IC fabrication technology. Prior to that, he was Director of Technology Development & Quality Systems at Texas Instruments. There he developed and applied high speed analog BiCMOS manufacturing technologies to products used in high capacity storage systems, wireless communication components, and PC processor interfaces. Earlier in his career he developed CMOS logic and non-volatile memory technologies, and managed pilot fabrication lines at NCR Microelectronics and Philips Semiconductors. In his initial career assignment at Hughes Aircraft he fabricated a space qualified image sensor subsequently used for Earth Resources imaging on the Landsat IV Satellite. He has been active in promoting nanotechnology by organizing forums and speaking on the subject. He has published related on-line articles. Since 2005 he has held multiple Chapter officer positions for the San Francisco Bay Area IEEE Nanotechnology Council Chapter. As an NSF peer reviewer he continues to support investments in small high tech businesses. Mr. Massetti holds a Master of Science degree in Applied Solid State Physics from the University of California, San Diego. He also earned his Bachelor of Science degree in Physics at St. Mary’s College of California.

Ira Feldman – Mr. Feldman is the principal consultant at Feldman Engineering Corp., where he manages and develops unique high technology solutions and business strategies. As a successful executive, he has proven his leadership ability to resolve product management and engineering challenges within organizations as well as with their supply chain and customers. Mr. Feldman’s broad knowledge and management experience with high volume manufacturing of complex technology products is the result of his extensive expertise in the semiconductor test and computer test industries. As Vice President of Business Development for Microfabrica, he identified and successfully brought to market many new applications for their EFAB technology (which is a breakthrough platform that enables the creation of sub-millimeter, 3D, fully-assembled micro-machines and precision parts of unprecedented scale and performance). Previously, at the probe card manufacturer NanoNexus, he was the Director of Products and Applications and the Director of Design Engineering. He managed a global team of engineers at Agilent Technologies (now Verigy/Advantest) that integrated Automatic Test Equipment (ATE) into end customers’ high volume manufacturing facilities prior to that. At Hewlett-Packard, at the star of his career, he drove the successful manufacturing introduction and ramp up of several generations of high-end mini-computers. He earned both a BS in Engineering and a Master of Engineering degree from Harvey Mudd College. And he publishes his “High Technology Business Development” blog which often covers nanotechnology, MEMS, semiconductor, and test topics.

 

Jeongwon Park – Dr. Park is senior research scientist in the Advanced Technologies Group, Office of the CTO Group, at Applied Materials, USA. He is an adjunct professor in the department of electrical engineering at Santa Clara University. He received a PhD from the University of California, San Diego in Materials Science and Engineering in 2008. His expertise is in nano-materials including CNT and graphene, nano-electronics, III-V semiconductor and Silicon Integrated Circuit processing coupled with a strong background in design and test. In addition to the industrial affiliations, he is currently involved with a close collaboration program with Stanford EE faculty members (Profs. Saraswat, Nishi, Phillip Wong, etc), MIT and UC Berkeley though his position at Applied Materials. His teaching efforts at Santa Clara include graduate level coursework on: “Fundamentals of Semiconductor Physics”, “Nanoelectronics”, “Nanotechnology”, “Nanomaterials”, etc in the Electrical Engineering Department at Santa Clara University. During his PhD, he focused on nanoelectronics with carbon nanotubes and organic field effect transistors including fabrication within a clean room, experience with CMOS, MEMS, packaging, device processing/measurements, simulations and modeling tools. These supplemental areas of focus and his continued interest and study of epitaxial Si, SiGe, III-V cleaning, Carbon Nanotube, Graphene, and similar materials have been on-going in parallel with his professional career.  He has been a guest researcher at NASA Ames Research Center, Lawrence Berkeley National Labs(LBNL), and Sun Microsystems, in addition to his work at UCSD, Hanyang University, Institute for Advanced Engineering, and Seoul National University in Korea. He has published more than twenty papers.

 

Jianhua (Joshua) Yang – Dr. Yang is Principal Research Scientist at HP Labs, leading the ReRAM (Memristor) device study effort. His current research interest is Nanoelectronics and Nanoionics, especially for memory and computing applications, where he authored and co-authored over 100 papers in academic journals and international conferences, and holds 15 granted and over 60 pending US Patents. In the last 3 years, he has been invited to international conferences or universities to give over 20 keynote speeches, invited talks, or seminars. He recently guest-edited two journal special issues on Non-volatile Memory technologies for Nanotechnology and Applied Physics A, respectively. He also serves as a co-editor of Applied Physics A. He obtained his PhD from the University of Wisconsin – Madison in Material Science Program in 2006 and joined HP at that time.