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Archive for the ‘IEEE Milestones’ Category

Mar 10 – High-Power Microwave Tube Development at Stanford and SLAC

Thursday, December 10th, 2015

Thursday, March 10, 2016
6:00 PM: Doors open for refreshments and networking
6:30 PM: Panel presentation

 

Registration Required, donation suggested
Click Here To Register and pre-donate
Bring ticket to meeting

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Venue: KeyPoint Credit Union
2805 Bowers Ave (just off Central Expressway)
Santa Clara, CA 95051

Park in lot adjacent to building on Bowers Ave.

Our Thanks To KeyPoint Credit Union

IEEE SV Tech History committee is extremely grateful to KeyPoint Credit Union for use of their auditorium as our prime venue. Many thanks to Doron Noyman of KeyPoint for his support in making that happen.
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Abstract:
The SF Bay Area has been a hotbed to technology development since the beginning of the 20th century. In this interview panel meeting, you’ll hear how Sigurd and Russell Varian came up with the plans for the klystron at Stanford in the late ’30’s, with critical theoretical contributions from Bill Hansen, physics professor. With a focus on Hansen, we’ll see how the theory and practice of microwave tubes developed locally during and after WW II, resulting in small linear accelerators, and eventually into the 2-mile-long Stanford Linear Accelerator, out behind the campus. The klystron and linear accelerator technology is still in use today around the world, as the prime radiation treatment for cancer.

Dave Leeson is in the final stages of a two-volume book on the life and career of Bill Hansen; he’ll give us ‘inside information’ about those early days, and how this breakthrough happened. Richard Winkler built the first 1-MW klystrons for his Stanford degree thesis, and will discuss their construction in the mid-50’s.  Allen Odian describes how the Stanford Linear Accelerator Center (SLAC) got started, some stories about Panofsky, and “first-beam”.  Burton Richter will tell of the early days of SLAC, and stories of how it was constructed and used. he’ll conclude with some of the physics experiments leading up to his Nobel Prize in 1976.

SLAC was the first of the many IEEE milestones dedicated in the SF Bay area

Join us for an interview of Profs. David Leeson and Burton Richter, as Paul Wesling, IEEE Life Fellow, explores this Silicon Valley technology

Panelists:

Prof. David Leeson, consulting professor of Electrical Engineering at Stanford.
Prof. Leeson is finishing a book on Bill Hansen’s career and contributions.

Richard Winkler, Stanford Engr ’53.
Winkler worked on high-power klystrons at Stanford. He went to Shockley Transistor (became Cleavite) just after Noyce and Moore left, and was the first regular employee at SLAC, designing equipment to test the 50-MW klystrons, did klystrons for first medical uses of linear accelerators.

Dr. Allen Odian, PhD from MIT, Fulbright Scholar, Assoc Prof at Univ of Ill.
Dr. Odian joined SLAC in 1961 and was involved with detectors.

Prof. Burton Richter (tentative), Physical Sciences, Stanford, and Director Emeritus at SLAC
Prof. Richter began post-doc work at Stanford in 1956, becoming a professor in 1967, and designed the Stanford Positron-Electron Accelerating Ring (SPEAR). He succeeded Wolfgang “Pief” Panofsky as director of SLAC in 1984.  He shared the 1976 Nobel Prize in Physics for his work on the particle that has been dubbed J/psi.

Paul Wesling will moderate this meeting.

Oracle (Sun) to receive IEEE Milestone for SPARC architecture on Feb 13, 2015

Tuesday, January 20th, 2015

The  IEEE Milestone Award event recognizing the technological achievement of the SPARC RISC Architecture will be presented at 10am on Feb 13, 2015 at the Oracle Auditorium in Santa Clara, CA.   That’s one day after the UC Berkeley RISC Project milestone is presented as described in the previous post.   The plaque unveiling will be preceded by a dedication ceremony in the Oracle Auditorium beginning at 10:00 am with Bill Joy, Dave Patterson, Andy Bechtolsheim, all instrumental in the early success of the SPARC architecture, listed as planned speakers. IEEE President Howard Michel will also say a few words.  Over 200 IT professionals from throughout the Silicon Valley and beyond are expected to attend.

The Relevance of the SPARC Processor Architecture:

Sun Microsystems introduced SPARC (Scalable Processor Architecture) RISC (Reduced Instruction-Set Computing) in 1987. Building upon UC Berkeley RISC and Sun compiler and operating system developments, SPARC architecture was highly adaptable to evolving semiconductor, software, and system technology and user needs. Over the course of its life the SPARC processor architecture has powered millions of servers and workstations and is still a leading and highly valued technology. Today, Oracle continues to engineer new levels of excellence into the SPARC architecture delivering the highest performance scalable servers, for engineering, enterprise, Internet and cloud computing applications

The first SPARC processor debuted in 1986 and was the CPU for the Sun-4 workstation the following year. In 1992 Sun launched its first high-end SPARC server, the successful SPARCcenter 2000. Today, the SPARC processor family is used in Oracle’s enterprise servers to create architectures that are optimized for a powerful mix of application types, from CRM systems and Java/Web middleware infrastructure applications to mission-critical ERP and back-end OLTP/data warehousing enterprise applications that depend on high availability and scalability.

According to Wikipedia,  there have been three major revisions of the architecture. The first published revision was the 32-bit SPARC Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit “extended precision” floating-point arithmetic to 128-bit “quad-precision” arithmetic. SPARC V8 served as the basis for IEEE Standard 1754-1994, an IEEE standard for a 32-bit microprocessor architecture.  SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International in 1993. It was developed by the SPARC Architecture Committee consisting of Amdahl CorporationFujitsuICLLSI LogicMatsushitaPhilipsRoss TechnologySun Microsystems, and Texas Instruments.

A very interesting post titled SPARC History from 1987 to 2010 provides more history and background information.

You can register for the Feb 13th event here.

UC-Berkeley to receive IEEE Milestone for RISC Project on Feb 12, 2015

Friday, January 9th, 2015

The UC-Berkeley RISC milestone plaque will be unveiled at 3:30 PM Feb. 12, 2015 in the lobby on the 3rd floor of Soda Hall, Berkeley’s Computer Science building. Speakers will include IEEE 2015 President Howard Michel, Professor David Patterson, and several others.

The unveiling will be part of the program for UC-Berkeley’s annual one-day research program (BEARS) that is focused on current research.  Approximately 250 professionals from Silicon Valley and elsewhere will attend. Many of those attendees likely will attend the brief unveiling ceremony and thereby fill the space in the lobby where the plaque will be displayed.

Relevance of the RISC research project:

UC-Berkeley students designed and built the first VLSI reduced instruction-set computer in 1981. The simplified instructions of RISC-I reduced the hardware for instruction decode and control, which enabled a flat 32-bit address space, a large set of registers, and pipelined execution. A good match to C programs and the Unix operating system, RISC-I influenced instruction sets widely used today, including those for game consoles, smartphones and tablets.

From Prof. David Hodges:

In the 1970s, the general trend in in computer design was to increase the complexity of computer architectures. The thought was that this would best exploit the rapidly advancing capabilities of semiconductor technology. The popular DEC VAX 11-780 was the leading example. About 280 machine-language instructions were implemented in the VAX hardware.  The VAX 11-780, a so-called super minicomputer, was advertised as exercising 1 million instructions/second and sold for about $100,000. This class of computers was then termed CISCs, or complex instruction set computers.

UC-Berkeley Professors David Patterson and Carlo Sequin observed that compilers for high-level computer languages, such as C, rarely utilized the added instructions. They thought that overall performance could be improved by optimizing the combination of processor function and memory on a single chip. Better overall performance at a much lower cost might be achieved by simplifying the processor, thereby allowing more chip area to be devoted to memory. Thus the goal was defined as a RISC, or reduced instruction set computer.

The RISC-I project was initiated in 1980 with assignments in a sequence of graduate classes at UC-Berkeley, aiming to validate the RISC hypothesis. Initial conclusions based on simulation were positive, so the project continued, with critical grant support from DARPA. Students designed a processor with just 31 instructions, each executed in a single clock cycle.  Included on the same student-designed chip, were 78 32-bit registers. This was enough memory to enable one-cycle execution of a large fraction of the instructions in compiled code.

Early in the project, the Berkeley team learned of previously unpublished work at IBM around 1975, led by Dr. John Cocke. The IBM 801, never commercialized, pioneered
architectural principles similar to those independently chosen by the Berkeley team, though the goals for the 801 were quite different. Dr. Cocke visited Berkeley in 1981 and spoke to the student-faculty team. He gave them enthusiastic encouragement for their undertaking.  The first student-designed RISC-I chips, realized via the DARPA and NSF-funded MOSIS implementation service, were received in the fall of 1981. They were functional, though with minor deficiencies. However, performance was sufficient to convince previous skeptics to recognize the merits of the RISC approach to design of very large scale integrated (VLSI) computing. After correction of minor design bugs, the RISC-I design proved to outperform the VAX on almost every real-world benchmark.

The biggest obstacle in 1980 was skepticism among knowledgeable professionals, friendly or otherwise. No one on the team had prior experience designing VLSI computer processor chips. Professors Patterson and Sequin had the courage to continue. Of course, the work would not have been possible without the major support of DARPA and MOSIS.   A related MIPS project, led by Prof. John Hennessey at Stanford, featured important attention to the role of the compiler in making best use of RISC processor resources. The first working chip resulting from that project came about a year after RISC-I at Berkeley.

The RISC design was first commercialized as the SPARC microprocessor, introduced in 1987.   Professor Patterson served as a consultant to Sun Microsystems, assisting Sun in

development of the powerful RISC-based SPARC workstations. The SPARC workstations became a leading tool in the design of integrated circuits. Sun Micro is now a part of the Oracle Corporation and will be receiving their own IEEE Milestone for SPARC on February 13, 2015.   A companion post will describe that event, the RISC roots of SPARC, and why it was significant.

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Separately, Advanced RISC Machines (ARM) in the UK developed a continuing series of VLSI RISC processor designs that now are produced under license by leading
semiconductor manufacturers of chips for use in game consoles, smart phones, and tablet computers.

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References:

1.  Patterson, David A., and David R. Ditzel, “The case for the reduced instruction set computer.” ACM SIGARCH Computer Architecture News 8.6 (1980): 25-33.

2. Patterson, David A., and Carlo H. Sequin, “RISC I: A reduced instruction set VLSI computer.” Proceedings of the 8th annual symposium on Computer Architecture, IEEE
Computer Society Press, 1981. Patterson, David A., and Carlo H. Sequin, “Design and Implementation of RISC I” UC Berkeley EECS Technical Report CSD-82-106, 1982. (Also appeared in Proc. Advanced Course on VLSI Architecture, University of Bristol, England, July 19-30, 1982.)

3.  Patterson, David A., and Carlo H. Sequin, “A VLSI RISC.” IEEE computer 15.9 (1982): 8-21.  Digital Object Identifier: 10.1109/MC.1982.1654133

4. Sherburne, R. W., Katevenis, M. G., Patterson, D. A., & Sequin, C. H. (1984), “A 32-bit NMOS microprocessor with a large register file,” Solid-State Circuits, IEEE Journal of,19(5), 682-689. Digital Object Identifier: 10.1109/JSSC.1984.1052208

5.  Patterson, David A. “Reduced instruction set computers.” Communications of the ACM 28.1 (1985): 8-21.

Panel Session on RISC vs CISC in Silicon Valley Race for Microprocessor Leadershiphttp://ithistory.org/blog/?p=1826

 

 

New IEEE Milestones Approved; Others in Progress

Thursday, May 29th, 2014

IEEE SV History co-Vice Chair-Brian Berg reports that several historical Electrical Engineering  & Computing milestones were approved by the IEEE Board of Directors this week:

  • 2013-03 First Breaking of Enigma Code by the Team of Polish Cipher Bureau, 1932-1939
  • 2013-16 First RISC Microprocessor, 1980-1982
  • 2013-06 SPARC RISC Architecture, 1987
  • 2013-28 Introduction of the Apple I Computer, 1976
  • 2013-22 Introduction of the Apple II Computer, 1977-1978
  • 2013-26 First generation and experimental proof of electromagnetic waves, 1886-1888

A complete list of IEEE milestones (including hotlinks for each) is at:

http://www.ieeeghn.org/wiki/index.php/Milestones:List_of_IEEE_Milestones

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In addition to those approved, several more milestones are in the pipeline.

  • Brian is hoping to have all the Macintosh info together by next week so that it can get voted on this fall.
  • Internet pioneer Vint Cerf (now with Google) has agreed to work on a milestone for TCP/IP, and he has an assistant helping him with that task.
  • RISC and SPARC milestones will likely be both dedicated during the same week in Feb. 2015.

We’ll continue to update this website with breaking news on IEEE milestones as well as tech history programs of interest.

 

 

Coverage of Apr 25, 2014 IEEE Milestone: Birth of the 1st PC OS=CP/M

Tuesday, April 29th, 2014

Many of these article links are courtesy of April 25th IEEE Milestone Event Master of Ceremonies Brian Berg:

1.  Article from Univ. of WA Computer Science and Engineering (The alma mater of Gary Kildall and Tom Rolander.  That’s where they met)

2. The Monterey NPR station played this interview 4 times on Thursday, April 24th.  This IEEE Milestone event  may get wider coverage, including next Friday’s California Report which is played by all Calif. NPR stations (KQED FM, Fri. at 6:30pm).  The NPR reporter was at the event.
3.  The Monterey Herald: Computer pioneer honored in Pacific Grove
4.  This iProgrammer posting – IEEE Honors Gary Kildall With Plaque – includes a link to a 28-minute video that chronicles the life of Kildall, and does a pretty good job of putting his accomplishments into perspective.
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May 5th Update from Brian Berg:
This KQED website posting includes the audio story played on Friday on KQED-FM 88.5.  KQED did a very nice job of combining portions of the KAZU story aired on Monterey’s NPR station before the dedication with the dedication itself.  The text on the website is great as well, and includes a photo of the plaque (see below) in the sidewalk at 801 Lighthouse Ave. in Pacific Grove.
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Pre-event postings:
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Photo’s courtesy of Doug Fairbairn (you must provide your name and email address to view photos):
Included in the photo’s are:
  •  IEEE President-Elect Howard Michel
  •  Event MC: Brian Berg, IEEE SV History Co-Chair
  •  Computer History Museum Semiconductor Curator and CP/M Milestone Champion David Laws
  •  Microprocessor Co-Inventor Ted Hoff  IEEE SV History Volunteer
  •  SCV Section Chair Ed Aoki
  •  Monterey Bay Sub-Section Chair Weilian Su
  •  R6 Director-Elect Tom Coughlin &  IEEE SV History Co-Chair
  •  IEEE Senior Historian John Vardalas
  •  Milestone Coordinator Dick Ahrons
  •  e-GRID Editor Paul Wesling & IEEE SV History Volunteer
  •  R6 Central Area Student Activities Chair Mostafa Mortezaie
  •  A few other IEEE members
  •  Former Digital Research employees Tom Rolander, Gordon Eubanks and Brian Halla
  •  Gary Kildall’s son Scott Kildall and daughter Kristin Kildall
  •  Asilomar Microcomputer Workshop Program Chair John Wharton
  •  Mayor and Vice Mayor of Pacific Grove
  •  2 Commanders from the Naval Postgraduate School where Gary Kildall taught
  •  A large contingent of former Digital Research employees
NOTE:  We are investigating how to upload more photos to this website and will do so ASAP!  In the meantime, here are links to the Memorial Plaque and a few more pics courtesy of Doug Faribairn of the Computer History Museum:
EEE Milestone Plaque
IEEE Milestone Plaque:  CP/M Microcomputer Operating System, 1974:
https://dl.dropboxusercontent.com/u/66417074/Camera%20Uploads/2014-02-07%2011.59.06.jpg
Group photo:
https://dl.dropboxusercontent.com/u/66417074/Camera%20Uploads/2014-02-07%2011.59.06.jpg
Photo of Howard Michel, IEEE President-elect (2014) on right, and David  Laws, Proposer of this Milestone and Semiconductor Curator at the Computer History Museum on left:
https://dl.dropboxusercontent.com/u/66417074/Camera%20Uploads/2014-04-28%2017.31.40.jpg
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June 6th update from CHM’s David Laws:
The video of the IEEE CP/M Milestone plaque dedication event is now posted on the Computer History Museum YouTube Channel under the title “The Legacy of Gary Kildall: The IEEE Milestone Plaque Dedication” at:
https://www.youtube.com/watch?v=HO6IPpL0y8g&list=UUHDr4RtxwA1KqKGwxgdK4Vg

The video is about 1 hr and 40 min total. It includes the presentations in Pacific Grove City Hall and the unveiling of the plaque outside 801 Lighthouse Avenue. The speakers and times of their first comments are:
Robert Huitt 1:00
Brian Berg 2:15
Howard Michel 12:16
David Laws 21:44
Tom Rolander 26:50
Gordon Eubanks 29:00
Brian Halla 56:35
John Wharton 1:07:00
Scott Kildall 1:27:45
Bill Kampe 1:35:30

If you lose the URL link go to YouTube and search for “gary kildall ieee”

Thanks to everyone who participated and to Casey Rowson for the video recording and editing.

Other links related to the event include:
The IEEE Milestone page:
http://www.ieeeghn.org/wiki/index.php/Milestones:The_CP/M_Microcomputer_Operating_System,_1974
Museum Kildall article:
http://www.computerhistory.org/atchm/gary-kildall-40th-anniversary-of-the-birth-of-the-pc-operating-system/
Facebook page:
https://www.facebook.com/KildallLegacy
NPR broadcast:
http://kazu.org/post/recognizing-legacy-pacific-grove-inventor-gary-kildall

David Laws

Approved IEEE Milestone: Birth of the 1st PC Operating System (CP/M)

Thursday, January 23rd, 2014

Dedication of IEEE Milestone for Gary Kildall’s CP/M Microcomputer Operating System

The events on the afternoon of Friday, April 25, 2014, are open to the public. Plans for the IEEE Milestone dedication and unveiling are as follows:

2:00 PM – 3:30 PM Pacific Grove City Chambers, 300 Forest Ave.

Introductions by Mayor Bill Kampe, President-Elect of IEEE Howard Michels, and other dignitaries.

Overview of IEEE Milestone program.

A conversation with former DRI VP of Operating Systems Tom Rolander and Gordon Eubanks VP of Languages and Tools followed by Q &A session.

4:00 – 4:30 PM 801 Lighthouse Ave.

Street side plaque unveiling and brief remarks by representatives of the City, the IEEE, and others

4:30 – 6:00 PM 734 Lighthouse Ave. (Former DRI Engineering building)

Reception with light refreshments for AMW, IEEE and DRI alumni and friends

http://www.e-grid.net/docs/1404-milestone.pdf

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Backgrounder:

Gary A. Kildall, PhD (1942 – 1994),  developed and then demonstrated the first working prototype of CP/M (Control Program for Microcomputers) in Pacific Grove in 1974. Together with his invention of the BIOS (Basic Input Output System), Kildall’s operating system allowed a microprocessor-based computer to communicate with a disk drive storage unit and provided an important foundation for the personal computer revolution.   This article reviews the history of CP/M and why it was so important…………….

Read more at:  http://ithistory.org/blog/?p=2071

Readers are invited to leave a comment in box below the article.

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Reference:

The SF Chronicle website has information about the CP/M Milestone dedication event:

 

 

IEEE SCV Milestones 2013 Progress Report

Friday, December 6th, 2013

IEEE SCV Milestones Chair Dick Ahrons reported that three of nine proposed milestones have been approved by the IEEE History Committee.  They are: Ampex (Magnetic Storage pioneer in Redwood City, CA), CP/M (one of the first operating systems used by microprocessors and PCs; Gary Kildall of Digital Research, Pacific Grove, CA), and Shockley Labs (the birthplace of Silicon Valley).

Other milestones in progress include:  SUN SPARC micro, Intel 386 micro, Intel 4004 micro, Apple Mac/I/II PCs

Each of the completed milestone recipients will get a placque which will be placed in an agreed upon location.

IEEE SV Tech History committee will post upcoming announcements of Milestone events (as they occur) on this website.