IEEE

Archive for the ‘Past Committee Events’ Category

Sep 8 – Atari’s Impact on Silicon Valley: 1972-84

Wednesday, August 3rd, 2016

Thursday, September 8, 2016 – 6:30-8:30pm

6:00 PM: Doors open for refreshments and networking
6:30 PM: Panel presentation

SOLD OUT


Venue: KeyPoint Credit Union,

2805 Bowers Ave., Santa Clara 95051
(Just south of Central Expressway)

Park in lot adjacent to building on Bowers Ave.

Our Thanks To KeyPoint Credit Union

IEEE SV Tech History committee is extremely grateful to KeyPoint Credit Union for use of their auditorium as our prime venue. Many thanks to Doron Noyman of KeyPoint for his support in making that happen.


Abstract:

In the 1970s, Silicon Valley was a very different place.  There were few consumer companies.  Companies were started by PhDs and seasoned business people.  The value of a company was measured in the depth of its patent portfolio or its profits.  Venture money went to companies that solved difficult technology problems.

HP gave us the story of how a couple of young engineers started in a garage and built a major company over a 25-year period. Atari modified that story: a couple of young engineers started in a garage and built a major consumer company in less than 10 years, while having a blast doing it.  The Atari story was the basis for Apple and many of the major valley companies that followed.

Atari, founded in 1972 by Nolan Bushnell, Ted Dabney and Al Alcorn, created the earliest successful arcade and home video games, as well as early personal computers.  This event will include stories about products such as Pong and the Atari 2600, as well as the fun and turmoil surrounding this corner of Silicon Valley from 1972 to 1984.


Participants:

Nolan Bushnell, the legendary Silicon Valley entrepreneur who co-founded Atari in 1972, was a founding father of the video game industry, and was named by Newsweek as one of “50 Men Who Changed America.”

Al Alcorn: Atari employee #3 who designed Pong (the first commercially successful coin-operated video game), built the first video game on a custom chip (home Pong), and led the development of the Atari VCS home video game machine which launched the cartridge video game industry.

Owen Rubin: early coin-op engineer who helped in the transition from all-TTL games to microprocessor-based games.

Steven Mayer: chief Atari architect for home video games and computer systems, and who was on the team that brought Activision back from bankruptcy to become the world’s largest independent game’s software company.

Brian Berg, IEEE Silicon Valley History Committee Chair, will moderate this panel.

Ken Pyle, Managing Editor of Viodi, is videographer for this event.

May 25 – Flash: How Silicon Valley Enabled the Mobile Computing Revolution

Friday, May 20th, 2016

Wednesday , May 25,  2016
Doors open at 7:15
Presentation at 7:30

Sponsored with the Saratoga Historical Society
(
Potluck for members starting at 6:30)

$5.00 Donation Requested (at door)
Saratoga Historical Society members attend the lecture for free

Venue: (not our usual venue)

Foothill Club
20399 Park Place
Saratoga 95070

Abstract:

This presentation will discuss the origins of the mobile computing revolution in terms that anyone in attendance will understand and enjoy. The story starts at Bell Labs in New Jersey in the 1940s, transitions to the birth of Silicon Valley in 1956, and shows how Sputnik and the creation of the first Silicon Valley start-up led to an amazing series of inventions.

Computer storage consultant Brian Berg will lead this talk, and will interview SanDisk founder Dr. Eli Harari. You will learn about the ubiquitous importance of Moore’s Law in an environment of start-up companies, and about how Dr. Harari’s tenacity and inventions played a decisive role in enabling today’s handheld computing devices to access the world’s data. Both Brian and Eli are Saratoga residents.

More information

Mar 10 – High-Power Microwave Tube Development at Stanford and SLAC

Thursday, December 10th, 2015

Thursday, March 10, 2016
6:00 PM: Doors open for refreshments and networking
6:30 PM: Panel presentation

 

Registration Required, donation suggested
Click Here To Register and pre-donate
Bring ticket to meeting

…………………………………………………………………………
Venue: KeyPoint Credit Union
2805 Bowers Ave (just off Central Expressway)
Santa Clara, CA 95051

Park in lot adjacent to building on Bowers Ave.

Our Thanks To KeyPoint Credit Union

IEEE SV Tech History committee is extremely grateful to KeyPoint Credit Union for use of their auditorium as our prime venue. Many thanks to Doron Noyman of KeyPoint for his support in making that happen.
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Abstract:
The SF Bay Area has been a hotbed to technology development since the beginning of the 20th century. In this interview panel meeting, you’ll hear how Sigurd and Russell Varian came up with the plans for the klystron at Stanford in the late ’30’s, with critical theoretical contributions from Bill Hansen, physics professor. With a focus on Hansen, we’ll see how the theory and practice of microwave tubes developed locally during and after WW II, resulting in small linear accelerators, and eventually into the 2-mile-long Stanford Linear Accelerator, out behind the campus. The klystron and linear accelerator technology is still in use today around the world, as the prime radiation treatment for cancer.

Dave Leeson is in the final stages of a two-volume book on the life and career of Bill Hansen; he’ll give us ‘inside information’ about those early days, and how this breakthrough happened. Richard Winkler built the first 1-MW klystrons for his Stanford degree thesis, and will discuss their construction in the mid-50’s.  Allen Odian describes how the Stanford Linear Accelerator Center (SLAC) got started, some stories about Panofsky, and “first-beam”.  Burton Richter will tell of the early days of SLAC, and stories of how it was constructed and used. he’ll conclude with some of the physics experiments leading up to his Nobel Prize in 1976.

SLAC was the first of the many IEEE milestones dedicated in the SF Bay area

Join us for an interview of Profs. David Leeson and Burton Richter, as Paul Wesling, IEEE Life Fellow, explores this Silicon Valley technology

Panelists:

Prof. David Leeson, consulting professor of Electrical Engineering at Stanford.
Prof. Leeson is finishing a book on Bill Hansen’s career and contributions.

Richard Winkler, Stanford Engr ’53.
Winkler worked on high-power klystrons at Stanford. He went to Shockley Transistor (became Cleavite) just after Noyce and Moore left, and was the first regular employee at SLAC, designing equipment to test the 50-MW klystrons, did klystrons for first medical uses of linear accelerators.

Dr. Allen Odian, PhD from MIT, Fulbright Scholar, Assoc Prof at Univ of Ill.
Dr. Odian joined SLAC in 1961 and was involved with detectors.

Prof. Burton Richter (tentative), Physical Sciences, Stanford, and Director Emeritus at SLAC
Prof. Richter began post-doc work at Stanford in 1956, becoming a professor in 1967, and designed the Stanford Positron-Electron Accelerating Ring (SPEAR). He succeeded Wolfgang “Pief” Panofsky as director of SLAC in 1984.  He shared the 1976 Nobel Prize in Physics for his work on the particle that has been dubbed J/psi.

Paul Wesling will moderate this meeting.

Jan 14 – Lockheed: A Silicon Valley Strategic Defense Startup

Thursday, December 10th, 2015

Time & Date: 6pm-8:30pm, Thursday, Jan 14, 2016

 

Registration Required, donation suggested
Click Here To Register and pre-donate
Bring ticket to meeting


Venue: KeyPoint Credit Union
2805 Bowers Ave (just off Central Expressway)
Santa Clara, CA 95051

Park in lot adjacent to building on Bowers Ave.

Our Thanks To KeyPoint Credit Union

IEEE SV Tech History committee is extremely grateful to KeyPoint Credit Union for use of their auditorium as our prime venue. Many thanks to Doron Noyman of KeyPoint for his support in making that happen.
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Abstract:

In 1956 Lockheed moved its new division, Lockheed Missile Systems Division to a 275 acre site next to Moffett Field in Sunnyvale; Lockheed had been selected as the systems manager for the Navy’s Polaris Fleet Ballistic Missile and the developer of the missile itself. Lockheed in Silicon Valley went from zero employees in 1956 to more than 28,000 by 1965, far greater growth than HP or Fairchild – perhaps it should have been “Defense Valley,” but that’s another story. Polaris was the first submarine launched ballistic missile in the US’s triad of nuclear defense systems. Extended thru four production generations (Polaris A1, A2 & A3 and Poseidon C3) it was retired from service in the early 1990s. They were followed by Trident I C4 and today’s Trident II D5.  Polaris/Poseidon and Trident, collectively known as the US Navy fleet ballistic missiles recently celebrated a sixtieth anniversary and  they are generally recognized as one of the most successful military industrial programs.

Join four three Lockheed senior leaders from then to get a retrospective on Defense Valley of the 1950s and 1960s and the Polaris/Poseidon program that led to today’s Tridents than make up the most secure leg of the strategic Triad.

Panelists:

Dave Montague a forty year Lockheed employee retired in 1996 as the President of the Missile Systems Division and a Corporate Vice President.  He came to Silicon Valley in 1957 as an engineer on the new Polaris program and progressed up the supervisory and management chain in guidance and control, systems engineering, and program management positions on Polaris, Poseidon, Trident 1, to executive management of Tactical and Defense systems and Trident II as well as several compartmented programs. He is a fellow of the AIAA and a member of the National Academy of Engineering.  He graduated from Cornell University in 1956

Cliff Kancler  a forty two year Lockheed employee retired in 2007.  Starting in 1965 in Silicon Valley with work on the first digital flight control computer Cliff was a major contributor in computer architecture development for guidance computers and for tactical and defense interceptor computers.  In addition to being part of our strategic defense systems computers from Cliff’s group are circling the solar system and have helped explore the moon.  He has earned recognition as a LM fellow and has a number of patents, and awards. He graduated Rensselaer Polytechnic Institute (RPI) in 1965.

Roy Dreisbach a thirty seven year Lockheed employee retired in 1997.  Upon graduating Menlo College in 1960 Roy joined Lockheed and held senior administrative assignments in Missile Systems, Research and Development, Advanced System, and Space Systems Divisions spanning programs such as Polaris A1 through Trident II as well as Tactical and Defense Systems.  He is an ex-naval aviator, having flown Lockheed Super Constellation early warning aircraft from 1954 to 1958.

Charlie Barndt is a forty eight year Lockheed Martin active employee. Upon graduating from Cornell University in 1965 Charlie joined General Electric as an engineer on Polaris and Poseidon. In 1967 he joined Lockheed as an engineer on Poseidon and Trident I. He progressed up the supervisory and management chain in missile electronics system and subsystems architecture and design, and was a major contributor on Trident II. Charlie is currently serving a third term as a Lockheed Martin Fellow for which he earned initial recognition in 2009. He is a recipient of the US Navy FBM Exceptional Achievement Award, and the Director of Strategic Systems Programs has recognized his 50 years of service in support of the US Navy FBM Program.

Moderator Tom Gardner from the valley’s storage industry would prefer call it the “Iron Oxide Valley,” but has learned much about Defense Valley preparing for this panel.

June 1 mtg: EDA’s pivotal role in development of fabless semiconductor industry

Monday, April 20th, 2015

Time & Date:  6pm-8:30pm  June 1, 2015
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Venue:   KeyPoint Credit Union
2805 Bowers Ave (just off Central Expressway)
Santa Clara, CA 95051

Park in lot adjacent to building  on Bowers Ave.

Note of Appreciation:  IEEE SV Tech History committee is extremely grateful to KeyPoint Credit Union for use of their auditorium as our prime venue.   Many thanks to Doron Noyman of KeyPoint for his support in making that happen.
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Abstract:

Electronic Design Automation (EDA) for LSI/VLSI Integrated Circuits not only helped meet the challenge of designing systems on a chip (SoC), but also played a crucial enabling role in development of the fabless model that’s so pervasive in today’s semiconductor industry.  EDA allowed system engineers to design chips and gave companies flexibility in targeting an IC design to available semiconductor fabs for manufacturing LSI and VLSI chips.

Companies like Cirrus Logic, Chips & Technologies, and Xilinx were among the first to “truly” separate the design of chips from their manufacturing in the mid 1980’s.  Prior to that time, each semiconductor company had their own silicon waver fabrication plant(s).  Both small and large leading edge semiconductor companies exploit the fabless semiconductor business model today.

This panel will recount the developments in EDA that took place from mid 1970’s to end of 1980’s and share with the audience their insights into how EDA helped transform the semiconductor industry into the fabless semiconductor mode.

Panelists:  

  • Suhas Patil, Cirrus Logic
  • Aart de Geus, Synopsys
  • Doug Fairbairn, VLSI Technology

Panel Moderator:   Alan J Weissberger, Chair-IEEE SV Tech History Committee

Bio’s of Panelists:

1. Suhas S. Patil, ScD EE

Suhas Patil is founder and retired Chairman of Cirrus Logic, Inc. a leading semiconductor company in US. He is co-founder of The Indus Entrepreneurs (TIE) world’s largest nonprofit for fostering entrepreneurs and served as its founding president.

Before becoming an entrepreneur, Dr. Patil was Assistant Professor of Electrical Engineering (EE) at MIT where from 1972 to 1974 he also served as Assistant Director of Project MAC (Multi-Access Computer), where leading edge work was done on time-sharing and on line computer systems.  In 1966 Prof. Patil developed one of the first on line information management systems for the department of Electrical Engineering at MIT.   From 1975 to 1980 Dr. Patil was an Associate Professor of Computer Science at University of Utah where he started the VLSI (very large-scale integrated circuits) group and worked on design methodology for design of complex integrated circuits.

In 1980 Dr. Patil started Patil Systems, Inc. a semiconductor company based on his academic work in design automation of IC. In 1984 this company moved to Silicon Valley from Salt Lake City, Utah and changed its name to Cirrus Logic, Inc. High volume commercial SoC chips for set top units developed at Patil Systems, Inc. in early 1980 showed viability the fabless model of semiconductor industry.

Suhas received the Doctor of Science degree (ScD) in Electrical Engineering from MIT in 1970.  In 1995 Indian Institute of Technology (IIT), Kharagpur conferred Honorary Doctor of Science degree on Suhas for his work in science and industry.  He served on the board of trustee of The Computer History Museum, The Tech and the World Affairs Council of Northern California from. In February, 2003 Dr Patil was named Life Fellow of Indian Institute of Technology, Kharagpur.

2.  Aart de Geus, PhD EE

Aart de Geus is the founder, chairman and CEO of Synopsys Inc. He is a fellow of the IEEE and a Phil Kaufman Award award winner.  Aart received  a PhD in EE from Southern Methodist University, Texas, USA.

Since co-founding Synopsys in 1986, Dr. de Geus has expanded Synopsys from a start-up synthesis company to a global high tech leader. Long considered a pioneer in our industry, he’s been recognized for his technical, business and community achievements with multiple awards, including Electronic Business Magazine’s “CEO of the Year,” the IEEE Robert N. Noyce Medal, the GSA Morris Chang Exemplary Leadership Award, the Silicon Valley Engineering Council Hall of Fame Award, and the SVLG Life-time Achievement Award. He serves on the Boards of the Silicon Valley Leadership Group, Applied Materials, the Global Semiconductor Alliance, and the Electronic Design Automation Consortium.

3.  Doug Fairbairn, MSEE

Doug Fairbairn is Staff Director at the Computer History Museum and also his own photography business – Douglas Fairbairn Photography.   Doug earned a BS/MSEE at Stanford in 1971.  After graduation, Doug joined Xerox PARC as a systems engineer. While at PARC, he teamed up with Carver Mead and Lynn Conway to help develop the Mead Conway VLSI design methodology.

Leveraging that work, he formed VLSI Design Magazine (Lambda at the time) and was a co-founder of VLSI Technology in 1980. At VLSI Doug managed its leading edge IC design tools and ASIC business units.

Doug left VLSI in 1990 to form Redwood Design Automation and was later a division manager at Cadence after its purchase of Redwood in 1994.  Since leaving Cadence in 1998, he has served on the Boards of Catalytic, Quickfilter, Simutech, and Verisity.  He joined CHM and formed his photography business in 2006.

About the Moderator:

Alan J Weissberger, ScD EE was hired by Fairchild Systems Technology in March of 1970 to work on CAD algorithms and software to automate the layout of printed circuit boards.  Fairchild wanted to sell such a tool to its semiconductor customers and use it internally for its Sentry IC Tester and the family of 8, 16, and 32 bit minicomputers (known internally as Sprint) it was developing at that time.  In Sept 1970 the minicomputer division was shut down and Weissberger was laid off without ever working on the CAD project.

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Time-line (for all our meetings held at KeyPoint):

6pm-6:30pm:        Networking and light dinner/non-alcoholic drinks ($5 donation requested)
6:30pm-6:35pm:   Opening Remarks & Introductions
6:35pm-8pm:        Panel Discussion
8pm-8:15pm:        Audience Q & A
8:15pm:                Appreciation & Adjournment; informal chit-chat with panelists
8:30pm:                Everyone must be out of the auditorium
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REGISTRATION REQUIRED:  Click here to register.

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Invitation to ask a question or comment:

If you’d like to submit a question or issue to discuss during the panel, please send email to: alan.weissberger@ieee.org  OR leave a comment in the box below this post.  There will be ~15 minutes for audience Q&A at the end of our panel discussion.

 

April 28th Meeting: How Did Hard Disk Drive Track Widths Get That Small?

Monday, March 2nd, 2015

Time & Date:  6:30pm-9pm  April 28, 2015

Venue:  

Western Digital, 1710 Automation Parkway, San Jose, CA 95131
Directions and Map 

For questions related to the Western Digital venue, please contact: Gerardo.Bertero@wdc.com

Registration Required
Click Here To Register
Bring ticket to meeting

 

Abstract:

Hard disk drives are all about higher storage capacity and that means higher areal density. Areal density is the product of linear density (density of bits along the tracks) and track density (density of tracks on the disk surface). In this IEEE SV History committee panel session we will examine how hard disk drive track widths have been reduced over over the last 50 years,  while continuing to be the storage behemoths that we still use today.

Over the 50 years of HDD history various ways have been used to try and reduce the track width of the recorded information.  These have included: improved servo technology, creating patterned tracks on the media surface, shingling recorded tracks and general improvements in head and media technology over time.  The panelists will be able to talk about all of these technologies and how they were trying to reduce HDD track width, increase the track density, and provide higher capacity mass storage products.

 

Moderator:  Tom Coughlin, Coughlin Associates (formerly with Seagate Technology, Maxtor, Micropolis, Ampex, Syquest and other companies)
Panelists:
  • Chris Bajorek, formerly at IBM and Komag
  • Dick Oswald, long time consultant
  • Ed Grochowski, formerly at IBM
  • Bruce Gurney, formerly at IBM and HGST

Timeline (this meeting only):

6:30pm  Networking Reception —   Donation Requested for food/drinks

7:00pm  Chair’s Opening Remarks

7:05pm  Introduction of the Topic by Tom Coughlin

7:15pm-8:30pm  Panel Discussion

8:30pm-8:50pm  Audience Q &A

8:50pm-8:55pm  Appreciation and Adjournment

 

April 16th Meeting @Ethernet Tech Summit: Fireside Chat with Larry Roberts

Sunday, March 1st, 2015

Time & Date:  2pm-3pm  April 16, 2015
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Venue:   Santa Clara Convention Center (Ethernet Tech Summit 2015)

Title: Fireside Chat with Internet Pioneer Larry Roberts

Organizer: Alan J. Weissberger, Chair, IEEE Silicon Valley Technology History Committee

Speaker: Larry Roberts, CEO/Co-Founder, TSL Technologies

Interviewer: Geoff Thompson, Principal, GraCaSi

Abstract:

What can we learn from the origins, emergence,and explosion of the now omnipresent Internet?  Join Internet pioneer (and ARPANET creator) Larry Roberts in exploring how the Internet came about, how it reached its present state, and where it is heading in the future.  This interview will cover both historical lessons and future trends.

Larry Roberts, PhD is best known as the leader of the team that created the ARPANET using packet switching techniques.  The ARPANET was later converted into the current Internet, hence making him one of the true founders of the Internet.  He has received many awards, including the National Academy of Engineering’s Charles Stark Draper Prize “for the development of the Internet”, the AFIP Harry Goode Memorial Award, and the IEEE 2000 Internet Award.  He is a member of the National Academy of Engineering and the American Academy of Arts and Sciences.  The founder and CEO of five telecommunications companies, he has developed many leading edge products to advance Internet capability, QoS, and reliability.  He holds 11 patents and has given invited presentations at many conferences worldwide.  He holds a PhD in electrical engineering, an MSEE, and a BSEE from MIT.

About the Interviewer:

Geoff Thompson is currently Principal at GraCaSi, where he serves as an advisor on networking standards development and a technical expert on intellectual property issues.  He has been a voting member of the IEEE 802.3 (Ethernet) committee for over 30 years and also serves as a Member Emeritus of the IEEE 802 Executive Committee.   He chaired the IEEE 802.3 Working Group and was later 1st Vice Chair of the 802 Executive Committee.  A long-time leader in standards development, he was a Distinguished Member, Technical Staff at Nortel Networks and a Consulting Member, Engineering Staff at Xerox.  Geoff has been a major contributor to the IEEE member discussion group, has participated in many ComSocSCV meetings and is the IEEE Silicon Valley Tech History committee officer in charge of LANs and the Internet. He holds a BSEE from Purdue University.

About the Organizer:

Alan J. Weissberger, ScD EE is the Chair of the IEEE Silicon Valley Technology History Committee, Content Manager for the global IEEE Communications Society (ComSoc) Community website, North America Correspondent for the IEEE Global Communications Newsletter, Chair Emeritus of the IEEE Santa Clara Valley (SCV) ComSoc, and an IEEE Senior Life Member.  He is a former Adjunct Professor in the Santa Clara University Electrical Engineering Department and taught 42 graduate courses there. As a volunteer for the Computer History Museum, SIGCIS.org, and ITHistory.org, he writes technical summaries of lectures and exhibits.  Alan is also a contributing author for the Viodi View.

 Note:  This is an OPEN session (free if you register on-line) at the Ethernet Tech Summit 2015.  Register here.

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Postcript:  

This history session went very well with a smooth flow between Geoff and Larry.  The Q & A was also quite good, except for a question about artificial intelligence in the Internet possibly make it think on its own.  Note that software control over the network does NOT imply artificial intelligence or any thinking machines.  It’s the big data/ analytics software in cloud resident computer servers that might be able to predict outcomes based on past behavior.

Glad we could give credit to Larry as the primary creator of the X.25 protocol and his leading role in commercializing Packet Switched Public Data Networks at Telenet (later sold to GTE).  Telenet was way ahead of AT&T, Sprint and other N.A. X.25 PSPDN carriers.  In the mid to late 1970s, his version of the X.25 protocol was accepted by what is now called BT (British Post Office then) and Orange (Transpac then).  It was later enhanced by ANSI X3S37 and CCITT SG XVII WP2 (which I participated in from 1978-1985).

—>X.25 was the only commercial and international public data network from 1976 to 1993 when the Internet went public and took over (see Larry’s comments below)!   Even ISDN used X.25 on both the B and D channels (Basic Rate access) for packet switching.

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Larry’s comments:

Alan,  What can I say? Your summary is very valuable as virtually no-one has realized that the developed world had a more reliable standardized packet service for almost 2 decades before the Internet.  As to the fireside chat, it went great as Geoff fed new questions to me whenever I stopped. It worked very well.

Another thought: The time slot of 1 hour for this fireside chat was a huge difference from a prepared speech and was a serious benefit in enabling us to cover a large amount of material over a long period of time (several decades).

Thanks,

Larry

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Thanks also to Paul Wesling for being the cameraman/videographer.  He and Ken Pyle will work to get the videos edited and captioned (with the help of Larry & Geoff for the latter).

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 alan.weissberger@ieee.org

 

 

April 1st meeting: “Silicon Valley” Semiconductor Industry from 1957-1975

Friday, February 20th, 2015

Time & Date:  6pm-8:30pm  April 1, 2015
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Venue:   Key Point Credit Union
2805 Bowers Ave (just off Central Expressway)
Santa Clara, CA 95051

Park in lot adjacent to building  on Bowers Ave.
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Panelists and their company/university affiliations from 1959 (or later)-1975:

  • Bernie Marren: Fairchild, Western Micro Technology, AMI, etc
  • Ted Hoff, Jr:  Stanford University (Researcher), Intel
  • Ed Pausa, Fairchild, National Semiconductor
  • David Laws:  Fairchild,  Litronix (LEDs), AMD

Moderator:  Alan J. Weissberger [Chair of IEEE SV Tech History Committee]:  Fairchild Systems Technology,  National Semiconductor, Signetics (9/76-to-9/79)
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Abstract:

What was the semiconductor industry like in greater Santa Clara County- “the Valley of Hearts Delight”- before the term “Silicon Valley” was coined?   Most of us know that it was Fairchild Semiconductor that started the activity after it’s founders left Shockley Semiconductor Laboratory.

We start our semiconductor journey in 1957,when the “traitorous eight” left Shockley Labs to start Fairchild Semiconductor. How did that happen and what was Bob Noyce’s role? What other semiconductor companies existed in Santa Clara Valley in the late ’50s and what became of them?

In 1959, the integrated circuit (IC) was co-invented separately by Bob Noyce (Fairchild) and Jack Kilby (TI).  What types of discrete components were being sold here from 1957-1962, before the IC was commercially available?  What were their applications (e.g. UHF tuners for TVs)?   Our panelists will address that issue and the general state of the electronics/semiconductor industry before the IC was commercially available (1961-1962).

Did you know that the guy who was hired by Bob Noyce at Fairchild to train engineers on a secret product (the IC) wasn’t even told what it was until it became commercially available two years later?  Bernie Marren will tell that intriguing story, which will be followed by many others.  The panel will address three distinct time periods:

  • 1957-1962   Discrete component (pre-IC) era: transistors, diodes, etc
  • 1962-1968   IC era: digital logic, SSI & MSI, logic families converge to TTL, etc
  • 1968-1975   LSI era:  memories/shift registers, custom LSI, LED displays, consumer electronics, microprocessor applications

Our seasoned semiconductor industry veterans will tell what it was like to work at various Silicon Valley semiconductor companies in the early to mid 1970’s (AMI, National Semiconductor, AMD, Litronix, Intel, etc).  They will share stories about some of the all time great semiconductor icons- like Bob Noyce, Gordon Moore, Charlie Spork, Jerry Sanders, Bob Widlar, Pierre Lamond, and others.

About the Panelists:

Bernie Marren was working on fuses for the Polaris missile at AVCO, before Bob Noyce hired him to work at Fairchild Semiconductor in 1960 to train sales engineers on a secret, undisclosed product (it’s a terrific story).  From 1972 to 1976, Bernie served as the President and Chief Executive Officer of American Microsystems, Inc. (AMI).  He founded and was the first President of SIA. and Western Microtechnology Inc.  (President and CEO from 1977 to 1994).

Marcian “Ted” Hoff, Jr. will describe the semiconductor and electronics courses he took as a PhD student at Stanford along with the electronics design contract work he did as a Post Doc from 1962-1968 before he joined Intel as employee #12.   He will also review selected semiconductor companies that were doing business here and provide an Intel competitors perspective on many of them. Finally, Ted will set the record straight on the main applications of microprocessors from 1971-1975 (and for years later).

Ed Pausa will recount the early days at both Fairchild and National Semiconductor where he rose to be Vice President International Manufacturing and Services from 1973-1990.   During his 45 years in the semiconductor industry Ed directed 33 plants and subsidiary companies in 18 foreign countries  and 11 plants in six US states.

David Laws began his Silicon Valley career at Fairchild in Mountain View in 1968. He later served at LED pioneer Litronix, at Advanced Micro Devices (AMD) for 12 years where his last role was Vice President Business development, and at Altera where he was Vice President of Marketing.  He is currently Semiconductor Curator at the Computer History Museum.  David will provide an insiders view of Advanced Micro Devices (AMD) and its larger than life founder- Jerry Sanders.  He will also engage in dialog with the other panelists about Fairchild’s role in creating so many semiconductor companies in Silicon Valley.

Note that three of our four panelists and the moderator all worked at Fairchild at some point in time.

About the Moderator:

From 1968 to early 1970, moderator Alan J Weissberger worked on real time, minicomputer controlled testing of ICs made by Raytheon Semiconductor in Mt View, CA.  He was co-responsible for a CPU design at Fairchild Systems Technology in 1970 and later worked as a full time employee of National Semiconductor (1973-1976) and Signetics (1976-1979) in the microprocessor/COPs division of those companies.  Alan is the founder and chairman of the IEEE Silicon Valley Tech History committee and a four decade + volunteer for IEEE.

References:

The Rise of Silicon Valley: From Shockley Labs to Fairchild Semiconductor

Who Coined the Term Silicon Valley?

Interview with Bernie Marren by Rob Walker

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Time-line (for all our meetings):

6pm-6:30pm:   Networking and light dinner/non-alcoholic drinks ($5 donation requested)
6:30pm-6:35pm:  Opening Remarks & Introductions
6:35pm-8pm:  Panel Discussion
8pm-8:15pm:  Audience Q & A
8:15pm:  Appreciation & Adjournment; informal chit-chat with panelists
8:30pm:  Everyone must be out of the auditorium
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REGISTRATION REQUIRED: Click here to register

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Invitation to ask a question or comment: If you’d like to submit a question or issue to discuss during the panel, please send email to: alan.weissberger@ieee.org  OR leave a comment in the box below this post.  There will be ~15 minutes for audience Q&A at the end of our panel discussion.

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Comments from David Laws:

  • We don’t know when the term “Silicon Valley” was “coined.” It appeared in print for the first time (as far as we know) on January 11, 1971 Electronic News article written by Don Heffler.
  • Silicon activity in the Valley began not at Fairchild in 1959 but at Shockley Semiconductor Laboratory, 391 San Antonio Road early in 1956.  [Note that this panel session doesn’t cover that earlier time period]
  • Many people built “integrated circuits” before Kilby and Noyce. They include Hawick (RCA 1953), Dill (IBM 1954), D’Asaro (Bell 1954), and Wallmark (RCA 1957). Kilby’s contribution (1958) was to show that it made sense to build resistors out of semiconductor material. Noyce described the concept of using Jean Hoerni’s planar process to build and manufacture an IC in January 1959 and Jay Last’s team built the first working unit on May 11, 1960.

SSI Commercial* Digital Logic Families with Commercial Introduction Dates:

  • Fairchild Micrologic (DCTL) – March 1961
  • TI Series 51 (DCTL) – October 1961
  • Ferranti Micro-NOR (DTL) – 1962
  • Motorola MECL 1 (ECL) – 1962
  • Signetics SE100 (DTL) – 1962
  • Fairchild 900 Series (RTL) – 1963
  • Sylvania SUHL (TTL) – 1963
  • Westinghouse 200 Series (DTL) – 1963
  • Fairchild 930 Series (DTL) – 1964
  • TI Series 53 (DTL) – 1964
  • TI Series 54 (TTL) – 1964
  • Sylvania SUHL II (TTL) – 1965
  • TI Series 70 (ECL) – 1965 (?)
  • Fairchild (CTL) – 1966
  • Motorola MECL II (ECL) – 1966
  • TI Series 74 (TTL) – 1966
  • Motorola MECL III (ECL) – 1968
  • RCA CD4000 (CMOS) – 1968
  • Motorola 10K (ECL) – 1971
  • TI Series 74S (Schottky TTL) – 1971
  • Fairchild 100K (ECL) – 1973 (?)
  • TI Series 74LS (Low-power Schottky TTL) – 1974 (?)
  • Fairchild 74F (Isoplanar TTL) – 1978

* Numerous custom SSI logic families (CML, DTL, ECL, TTL) were developed by mainframe computer manufacturers, including CDC, Honeywell, IBM, NCR, RCA, SDS, and Univac.

Sources:

http://www.vintchip.com/FLATPACK/TEXASINSTRUMENTS.html

http://www.computerhistory.org/semiconductor/timeline/1965-Custom.html

http://www.computerhistory.org/semiconductor/timeline/1963-TTL.html

http://www.computerhistory.org/semiconductor/timeline/1962-Apollo.html

http://www.computerhistory.org/semiconductor/timeline/1963-CMOS.html

http://www.computerhistory.org/semiconductor/timeline/1969-Schottky.html

http://en.wikipedia.org/wiki/Emitter-coupled_logic

http://en.wikipedia.org/wiki/7400_series

http://www.shmj.or.jp/english/integredcircuits/ic60s.html

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Comments from Ted Hoff, PhD:

1. Patent filings:

  • Kilby filed 2/8/1959–issued 6/23/1964
  • Hoerni filed 5/1/1959–issued 3/20/1962
  • Noyce filed 7/30/1959–issued 4/25/1961

2. Importance of planar transistor (Hoerni):

The planar transistor laid the foundation for the integrated circuit, but also the methods used to create the transistors led to gradients of impurities within critical areas of the transistor.  Those gradients tended to speed up the movement of the holes and electrons which in turn made faster devices–with many more applications.

3.  Experience designing with transistors and  integrated circuits (ICs):

At Stanford, we used quite a few 2N706 transistors in logic circuits—in bread boarding ways to realizing adaptive systems, and forinterfacing to our computers.  We had a bank of filters for processing speech and a TV camera for computer input. We also used germanium transistors for some computer interface circuits.

I didn’t really begin to use ICs until after joining Intel in 1968.  Prices were falling and performance improving.  TTL seemed to be the best choice based on ease of use, noise margins, etc.  With the availability of MSI, seemingly more available in TTL than other families, TTL really became the prefered way to make digital logic systems–at least until the microprocessor became available in late 1971.

4.  Semiconductor Memory competitors for Intel:

AMS was founded about the same time as Intel (July 1968), also to develop semiconductor memory.  Back East there was Cogar.  Some of the earliest competition seemed to be from MOSTEK in Dallas, Texas.

5.  History & Importance of Semiconductor Memories:

There was work going on in smaller memory chips, such as bipolar RAMs used to implement arrays of registers in a computer CPU.  Intel had a design specification from Honeywell that led to our 3101–a 16×4 SRAM.  In traveling with Intel sales and marketing people, I often heard customers express appreciation for the support that Intel provided–even if they did not think our IC memory chip was the best, they used it because they felt we would be there to help if they ran into a problem.

Shift registers were another area of interest.  Some companies required customers for shift registers to buy their logic circuits, e.g. TTL, from them to get shift register deliveries.  Intel, was not providing TTL, but got quite a lot of business in shift registers.

6.  Semiconductor memories driving Moore’s Law:

Memories were seen as a driving force in the implementation of Moore’s law, because their large production volumes helped debug the underlying semiconductor production processes, thus improving yields and implementing Gordon Moore’s projections.

7.  Intel Memory Systems:

Intel began its own memory systems development activity, building big box systems to be used with mainframe computers.

8.  Importance of static RAMs for microprocessor applications:

Once the microprocessor gained market traction, the static RAM products became more important than DRAMs.  Quite a few of the earlier computer hobbyist products made use of static RAMs, because they avoided the refresh circuitry (CAS, RAS, etc) needed when using DRAMs

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Dec 2 Meeting: Perspective from Stanford’s Silicon Valley Archives

Tuesday, November 11th, 2014
Time & Date:  6pm-8:30pm  December 2, 2014
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Venue (NOT Keypoint Credit Union this month):
Texas Instruments Building E Conference Center  
2900 Semiconductor Dr. Santa Clara, CA 95052
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Panelists:
  • Leslie Berlin, Stanford’s Project Historian & Author of Bob Noyce biography
  • Henry Lowood, Stanford’s Curator for History of Science & Technology Collections; Film & Media Collections
Moderator:  Alan J. Weissberger, Chair of IEEE SV Tech History Committee & IEEE Sr Life Member
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Abstract:
In 1984, the Stanford University Libraries started a project that was unique at the time -capturing and preserving documentation about the regional development of science, technology, and industry.  This project became the Silicon Valley Archives, which this year celebrates its 30th anniversary. The Silicon Valley Archives originated with Stanford collections, such as the papers of Frederick Terman, related to the development of Silicon Valley. It soon expanded to include corporate and individual records, such as the papers of the Varian Brothers and Douglas Engelbart.In this panel session, Henry Lowood and Leslie Berlin will introduce their work as historians and archivists of the Silicon Valley, both how they have gathered documentation and how they have written about topics such as the life and times of Bob Noyce (Leslie) and digital games (Henry).  Our two distinguished panelists will engage in conversation with the moderator about Stanford’s role in preserving Silicon Valley history.In particular, questions about their work, writing, and projects will be addressed.  Here’s a sample of what we’ll cover in Stanford’s efforts to research and record the history of Silicon Valley:
  • What is the process, method and procedure for doing authentic, historical technology research?
  • Why did Stanford University start and continue a Silicon Valley archives collection?
  • What is the Silicon Genesis Project and what videos are available?
  • What is it like to research a book on Bob Noyce or other key figures and moments in the history of the Valley?
  • What is the history of Stanford’s work in this area?
  • What is Stanford’s objective in maintaining this archive?
  • How to decide what to collect in the archives?
  • What is currently in the archive and how often are artifacts added and/or deleted?
  • Who uses the archives?
  • How does the archiving of born-digital materials work?
  • How is the staff documenting the big trends today: social, mobile, cloud, etc.
  • How might IEEE SV Tech History Committee co-operate with Stanford’s Silicon Valley Archives in the future?

Come to the December 2nd IEEE SV Tech History Committee meeting to get answers to the above questions and much, much more. There will be ample time for audience Q & A after conclusion of the panel discussion.


Panelists Biographies:

Leslie Berlin, PhD has been studying the history of innovation in Silicon Valley for nearly two decades. Leslie is Project Historian for the Silicon Valley Archives at Stanford University.  In this capacity, she works to find and preserve key papers and artifacts pertaining to the history of Silicon Valley. She also helps researchers, students, and others interested in using Stanford’s collections.   Ms. Berlin is the author of the widely acclaimed biography of Bob Noyce- The Man Behind the Microchip. She has also published numerous articles.  You can read more about her here.

Henry Lowood, PhD has been Stanford’s Curator for History of Science and Technology Collections since 1983 and also for Film & Media Studies since 2005. He has managed the Silicon Genesis project from its inception as part of Stanford’s Silicon Valley Collections. Mr Lowood has taught many university courses, is the author of dozens of publications and has contributed to numerous exhibits.   His complete CV is here.

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Time-line (for all our meetings):
  • 6pm-6:30pm:   Networking and light dinner ($5 donation requested)
  • 6:30pm-6:35pm:  Opening Remarks & Introductions
  • 6:35pm-8pm:  Panel Discussion
  • 8pm-8:15pm:  Audience Q & A
  • 8:15pm:  Appreciation & Adjournment
  • 8:30pm:  Everyone must be out of the auditorium

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REGISTRATION REQUIRED: Click here to register  (event is over)

Video of this outstanding event is here

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Materials Presented at Nov 5th Meeting

Video of Nov 5th Meeting



Postscript to Nov 5 Early History of Silicon Valley Panel Session: Moore’s Law

Friday, November 7th, 2014

Notices:

  • If  you’d like to join/leave our Event Notification email list, please send email requesting same to: brianberg@gmail.com.  To be removed from the list, please send email to Brian with Subject line=SV History UNSUBSCRIBE
  • If you have any comments, issues, suggestions, feedback related to our committee or this website, please email:  aweissberger@sbcglobal.net
  • Please check http://ithistory.org/blog for related tech history blogs by Ted Hoff, Gordon Moore and Alan Weissberger
  • The blog post below is a replica of email sent to our email list with selected reader comments appended.

Appreciation:

I hope those in attendance (97 total) enjoyed yesterday’s (Nov 5th) panel as much as I did. Paul, Ted and Norm did a superb job of telling many stories of what is now known as “Silicon Valley.”

Moore’s Law was not conceived at Intel:

In my closing remarks I noted that Moore’s law was responsible for almost all the advances in electronics over the last forty years.  Most people know that, but think that Moore’s law was conceived at Intel.  That’s wrong!  It was postulated in 1965, when Gordon Moore was still at Fairchild Semiconductor as R&D Director.  The “law” applied to both bipolar and MOS chips at the time.  Here are two references with embedded hyperlinks:
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While Fairchild did the ground breaking work on MOS LSI in the mid to late 1960s and all through the 70s, they were not successful in commercializing the technology (see rebuttal from CHM’s David Laws below).  
Most folks don’t even know Fairchild had an MOS development effort!   Fairchild had other secrets too.  Did you know that Fairchild Systems Technology was working on a MOS/LSI micro-controller for the Sentry IC Testers in 1969-1970?  
And that they were designing 8/16/31 bit minicomputers called “Sprint” from March to Sept of 1970 (when the department was shut down)?  [This author was one of two CPU designers, working on a microcode assembler and simulator.]
 
Another key point is that Intel transformed Moore’s law from a theory to reality in the early 1970s, starting with the 1103 1K DRAM.  The volume produced enabled the MOS process to scale to higher chip densities (# transistors per chip) such that Intel could develop custom chips (e.g. for Busicom) and later microprocessors such as the 4004, 8008 and 8080.
 
In the early and mid 1970s, no one believed that MOS LSI processors would ever be used as the CPU for computers- bipolar LSI bit slices were the solution for that.  Wrong again…as MOS circuit densities, speeds and (lower) power consumption all combined such that MOS overtook bipolar LSI and created the PC industry.  
 
From my summary of a recent Commonwealth Club event:  Author Michael Malone at the Commonwealth Club: The Story Behind Intel
“The most important thing Malone said during his talk (including the Q&A session) was that Intel was the “keeper of Moore’s law,” which has been responsible for almost all the advances in electronics for several decades.  That’s due to Intel being able to continue to  advance the state of the art in semiconductor processing and manufacturing which enables them to pack more transistors on a given die size, increase speed, and reduce power consumption.”
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Bottom line is that MOS digital circuits have followed Moore’s law for over 40 years.  Much later, flash memory did too.  But not analog ICs or bipolar LSIs.
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Comment from Paul Zander:
  • Moore’s Law started as an empirical observation.  It become entrenched as a business mandate by Intel and other companies.
  • In the early 1900’s various companies were rushing to use the new Marconi wireless to replace telegraph and telephone wires.
  • By the end of the 1900’s various companies were replacing the airwaves with cables for TV.   The word, wireless, has been applied to eliminating cables between nearby boxes, e.g. Bluetooth, Wi-Fi, etc.

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Contrary opinion from Tom Gardner:

For those interested in Moore’s Law might want to take a look at, “The Lives and Death of Moore’s Law” According to this author  (Ilkka Tuomi from Finland) as of 2002:

“Contrary to popular claims, it appears that the common versions of Moore’s Law have not been valid during the last decades.  As semiconductors are becoming important in economy and society, Moore’s Law is now becoming an increasingly misleading predictor of future developments.”

If anything it has become less relevant in the subsequent decade.

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Comments from David Laws:

Fairchild not successful at commercializing MOS LSIs:  Under Corrigan (CEO from 1975-79) Fairchild was quite successful in commercializing MOS technology, they shipped hundreds of millions of $ in revenue. His problem was the lack of successful proprietary products to generate sustainable profits. 

Fairchild annual reports for the 10 years from 1970 to 79 show total semiconductor sales of $2.6B. MOS comprised approximately $300M of that number. Products included 4K DRAMs, 8K EPROMs, and the F8, 3870 and 6800 microprocessors. According to a 1978 Dataquest report, Fairchild shipped 655 million units of the F8. Intel shipped 510M units of the 8080, and Motorola 435M units of the 6800. The company also had a digital watch division (they built models for Tiffany and others as well as their own brand) and a consumer video game business that used MOS devices. The latter’s major claim to fame was the introduction of the ROM-based game cartridge that was quickly adopted by Atari.

“Most folks don’t even know Fairchild had an MOS development effort!” – True. Even fewer know that Fairchild invented CMOS! See:http://www.computerhistory.org/semiconductor/timeline/1963-CMOS.html

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Comment from Ted Hoff, PhD- employee #12 at Intel in 1968:

Gordon always considered his work more of an observation than a law. It did provide an important guideline for determining the optimum complexity of ICs at a given point in time. In the early days of Intel, somewhere around 10% yield was about optimum, and applying Moore’s law helped meet that goal. Assuming 100 die sites per wafer, and a $50.00 processed wafer cost, each die would cost $5.00. Allowing $1.00 to package the die would result in a manufacturing cost of $6.00.  Sell it in quantity for $10.00 to $20.00 and you make a nice profit.

Double the size of the die, and you have less than 50 die sites, and yields around 1%. Each chip would cost more like $100 so you would need to charge more like $200-$300 for the same profit, and would likely be competing with SSI/MSI designs which were assumed to be on a PC board at $1.00 to $2.00 per IC. The higher price would probably discourage applications, so production volumes would be lower and there would be less improvement based on the learning curve.

Given Moore’s law, just wait a few years, and that more complex chip would be very manufacturable. In the past few years I have heard stories of perfect wafers–huge wafers of extremely complex chips running at 100% yield.

You can go the other way as well, assume half the die size and over 200 sites per wafer with abut 30% yield. Now the dice cost more like 80 cents each but if packaging still costs $1.00, the final cost is close to $2.00. It probably comes pretty close to the original total cost for the customer, but based on Moore’s law, it would soon become obsolete.

The advances in IC technology have helped reduce the cost of computing enormously, but there are still many areas where I think more computing progress might have been made–e.g. natural language processing, language translation, security, reliability, etc. Just because computer technology advances does not automatically help computer usage in certain areas.

Somewhere, someone needs to devote a lot of time working to solve those applications. Regarding IC design, the profits reaped by the semiconductor industry helped to motivate the IC industry to develop ever more capable tools and those tools helped reduce engineering costs. Standardization also helps reduce microprocessor design engineering cost, but helps in increasing applications for them. The effect is to move the engineering burden from microprocessor chip design to software and firmware development.

Alan, you were correct in noting that Moore’s original observation was made when he was at Fairchild. He considered that it applied to both MOS and bipolar designs. At Intel, most of the progress was made in MOS technology, although the Schottky bipolar design was a significant step in allowing bigger/more complex bipolar chips.

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Nov 5th Presentation slides Thanks to Paul Wesling for assembling this slide deck.
  • Nov 5th Videos (you can watch the entire video or individual video segments/”snippets” with captions). Thanks to Ken Pyle for creating these videos and Paul Wesling for reviewing and approving)

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Our next technical meeting is Dec 2nd: A conversation with Stanford’s Leslie Berlin and Henry Lowood will be at TI auditorium in Santa Clara, CA starting at 6pm with a networking reception/light dinner.

Dec 2 Meeting: Perspective from Stanford’s Silicon Valley Archives