UC-Berkeley to receive IEEE Milestone for RISC Project on Feb 12, 2015

The UC-Berkeley RISC milestone plaque will be unveiled at 3:30 PM Feb. 12, 2015 in the lobby on the 3rd floor of Soda Hall, Berkeley’s Computer Science building. Speakers will include IEEE 2015 President Howard Michel, Professor David Patterson, and several others.

The unveiling will be part of the program for UC-Berkeley’s annual one-day research program (BEARS) that is focused on current research.  Approximately 250 professionals from Silicon Valley and elsewhere will attend. Many of those attendees likely will attend the brief unveiling ceremony and thereby fill the space in the lobby where the plaque will be displayed.

Relevance of the RISC research project:

UC-Berkeley students designed and built the first VLSI reduced instruction-set computer in 1981. The simplified instructions of RISC-I reduced the hardware for instruction decode and control, which enabled a flat 32-bit address space, a large set of registers, and pipelined execution. A good match to C programs and the Unix operating system, RISC-I influenced instruction sets widely used today, including those for game consoles, smartphones and tablets.

From Prof. David Hodges:

In the 1970s, the general trend in in computer design was to increase the complexity of computer architectures. The thought was that this would best exploit the rapidly advancing capabilities of semiconductor technology. The popular DEC VAX 11-780 was the leading example. About 280 machine-language instructions were implemented in the VAX hardware.  The VAX 11-780, a so-called super minicomputer, was advertised as exercising 1 million instructions/second and sold for about $100,000. This class of computers was then termed CISCs, or complex instruction set computers.

UC-Berkeley Professors David Patterson and Carlo Sequin observed that compilers for high-level computer languages, such as C, rarely utilized the added instructions. They thought that overall performance could be improved by optimizing the combination of processor function and memory on a single chip. Better overall performance at a much lower cost might be achieved by simplifying the processor, thereby allowing more chip area to be devoted to memory. Thus the goal was defined as a RISC, or reduced instruction set computer.

The RISC-I project was initiated in 1980 with assignments in a sequence of graduate classes at UC-Berkeley, aiming to validate the RISC hypothesis. Initial conclusions based on simulation were positive, so the project continued, with critical grant support from DARPA. Students designed a processor with just 31 instructions, each executed in a single clock cycle.  Included on the same student-designed chip, were 78 32-bit registers. This was enough memory to enable one-cycle execution of a large fraction of the instructions in compiled code.

Early in the project, the Berkeley team learned of previously unpublished work at IBM around 1975, led by Dr. John Cocke. The IBM 801, never commercialized, pioneered
architectural principles similar to those independently chosen by the Berkeley team, though the goals for the 801 were quite different. Dr. Cocke visited Berkeley in 1981 and spoke to the student-faculty team. He gave them enthusiastic encouragement for their undertaking.  The first student-designed RISC-I chips, realized via the DARPA and NSF-funded MOSIS implementation service, were received in the fall of 1981. They were functional, though with minor deficiencies. However, performance was sufficient to convince previous skeptics to recognize the merits of the RISC approach to design of very large scale integrated (VLSI) computing. After correction of minor design bugs, the RISC-I design proved to outperform the VAX on almost every real-world benchmark.

The biggest obstacle in 1980 was skepticism among knowledgeable professionals, friendly or otherwise. No one on the team had prior experience designing VLSI computer processor chips. Professors Patterson and Sequin had the courage to continue. Of course, the work would not have been possible without the major support of DARPA and MOSIS.   A related MIPS project, led by Prof. John Hennessey at Stanford, featured important attention to the role of the compiler in making best use of RISC processor resources. The first working chip resulting from that project came about a year after RISC-I at Berkeley.

The RISC design was first commercialized as the SPARC microprocessor, introduced in 1987.   Professor Patterson served as a consultant to Sun Microsystems, assisting Sun in

development of the powerful RISC-based SPARC workstations. The SPARC workstations became a leading tool in the design of integrated circuits. Sun Micro is now a part of the Oracle Corporation and will be receiving their own IEEE Milestone for SPARC on February 13, 2015.   A companion post will describe that event, the RISC roots of SPARC, and why it was significant.


Separately, Advanced RISC Machines (ARM) in the UK developed a continuing series of VLSI RISC processor designs that now are produced under license by leading
semiconductor manufacturers of chips for use in game consoles, smart phones, and tablet computers.



1.  Patterson, David A., and David R. Ditzel, “The case for the reduced instruction set computer.” ACM SIGARCH Computer Architecture News 8.6 (1980): 25-33.

2. Patterson, David A., and Carlo H. Sequin, “RISC I: A reduced instruction set VLSI computer.” Proceedings of the 8th annual symposium on Computer Architecture, IEEE
Computer Society Press, 1981. Patterson, David A., and Carlo H. Sequin, “Design and Implementation of RISC I” UC Berkeley EECS Technical Report CSD-82-106, 1982. (Also appeared in Proc. Advanced Course on VLSI Architecture, University of Bristol, England, July 19-30, 1982.)

3.  Patterson, David A., and Carlo H. Sequin, “A VLSI RISC.” IEEE computer 15.9 (1982): 8-21.  Digital Object Identifier: 10.1109/MC.1982.1654133

4. Sherburne, R. W., Katevenis, M. G., Patterson, D. A., & Sequin, C. H. (1984), “A 32-bit NMOS microprocessor with a large register file,” Solid-State Circuits, IEEE Journal of,19(5), 682-689. Digital Object Identifier: 10.1109/JSSC.1984.1052208

5.  Patterson, David A. “Reduced instruction set computers.” Communications of the ACM 28.1 (1985): 8-21.

Panel Session on RISC vs CISC in Silicon Valley Race for Microprocessor Leadership



2 Responses to “UC-Berkeley to receive IEEE Milestone for RISC Project on Feb 12, 2015”

  1. […] UC-Berkeley to receive IEEE Milestone for RISC Project on Feb 12, 2015 […]

  2. Alan J Weissberger says:

    The video for this program is at:

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